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Searched refs:nv50 (Results 1 – 25 of 124) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_context.c60 struct nv50_context *nv50 = nv50_context(pipe); in nv50_memory_barrier() local
61 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_memory_barrier()
65 for (i = 0; i < nv50->num_vtxbufs; ++i) { in nv50_memory_barrier()
66 if (!nv50->vtxbuf[i].buffer.resource && !nv50->vtxbuf[i].is_user_buffer) in nv50_memory_barrier()
68 if (nv50->vtxbuf[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) in nv50_memory_barrier()
69 nv50->base.vbo_dirty = true; in nv50_memory_barrier()
72 for (s = 0; s < NV50_MAX_3D_SHADER_STAGES && !nv50->cb_dirty; ++s) { in nv50_memory_barrier()
73 uint32_t valid = nv50->constbuf_valid[s]; in nv50_memory_barrier()
75 while (valid && !nv50->cb_dirty) { in nv50_memory_barrier()
80 if (nv50->constbuf[s][i].user) in nv50_memory_barrier()
[all …]
Dnv50_state_validate.c20 nv50_validate_fb(struct nv50_context *nv50) in nv50_validate_fb() argument
22 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_validate_fb()
23 struct pipe_framebuffer_state *fb = &nv50->framebuffer; in nv50_validate_fb()
28 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB); in nv50_validate_fb()
71 nv50->rt_array_mode = array_mode | array_size; in nv50_validate_fb()
88 nv50->state.rt_serialize = true; in nv50_validate_fb()
93 BCTX_REFN(nv50->bufctx_3d, 3D_FB, &mt->base, WR); in nv50_validate_fb()
117 nv50->state.rt_serialize = true; in nv50_validate_fb()
121 BCTX_REFN(nv50->bufctx_3d, 3D_FB, &mt->base, WR); in nv50_validate_fb()
135 if (nv50->screen->tesla->oclass >= NVA3_3D_CLASS) { in nv50_validate_fb()
[all …]
Dnv50_shader_state.c35 nv50_constbufs_validate(struct nv50_context *nv50) in nv50_constbufs_validate() argument
37 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_constbufs_validate()
51 while (nv50->constbuf_dirty[s]) { in nv50_constbufs_validate()
52 const unsigned i = (unsigned)ffs(nv50->constbuf_dirty[s]) - 1; in nv50_constbufs_validate()
55 nv50->constbuf_dirty[s] &= ~(1 << i); in nv50_constbufs_validate()
57 if (nv50->constbuf[s][i].user) { in nv50_constbufs_validate()
60 unsigned words = nv50->constbuf[s][0].size / 4; in nv50_constbufs_validate()
65 if (!nv50->state.uniform_buffer_bound[s]) { in nv50_constbufs_validate()
66 nv50->state.uniform_buffer_bound[s] = true; in nv50_constbufs_validate()
77 PUSH_DATAp(push, &nv50->constbuf[s][0].u.data[start * 4], nr); in nv50_constbufs_validate()
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Dnv50_vbo.c142 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb, in nv50_emit_vtxattr() argument
145 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_emit_vtxattr()
174 if (attr == nv50->vertprog->vp.edgeflag) { in nv50_emit_vtxattr()
188 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi, in nv50_user_vbuf_range() argument
192 if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) { in nv50_user_vbuf_range()
193 const uint32_t div = nv50->vertex->min_instance_div[vbi]; in nv50_user_vbuf_range()
194 *base = nv50->instance_off * nv50->vtxbuf[vbi].stride; in nv50_user_vbuf_range()
195 *size = (nv50->instance_max / div) * nv50->vtxbuf[vbi].stride + in nv50_user_vbuf_range()
196 nv50->vertex->vb_access_size[vbi]; in nv50_user_vbuf_range()
199 assert(nv50->vb_elt_limit != ~0); in nv50_user_vbuf_range()
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Dnv50_state.c211 struct nv50_context *nv50 = nv50_context(pipe); in nv50_blend_state_bind() local
213 nv50->blend = hwcso; in nv50_blend_state_bind()
214 nv50->dirty_3d |= NV50_NEW_3D_BLEND; in nv50_blend_state_bind()
348 struct nv50_context *nv50 = nv50_context(pipe); in nv50_rasterizer_state_bind() local
350 nv50->rast = hwcso; in nv50_rasterizer_state_bind()
351 nv50->dirty_3d |= NV50_NEW_3D_RASTERIZER; in nv50_rasterizer_state_bind()
442 struct nv50_context *nv50 = nv50_context(pipe); in nv50_zsa_state_bind() local
444 nv50->zsa = hwcso; in nv50_zsa_state_bind()
445 nv50->dirty_3d |= NV50_NEW_3D_ZSA; in nv50_zsa_state_bind()
608 nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s, in nv50_stage_sampler_states_bind() argument
[all …]
Dnv50_compute.c169 nv50_compute_validate_samplers(struct nv50_context *nv50) in nv50_compute_validate_samplers() argument
171 bool need_flush = nv50_validate_tsc(nv50, NV50_SHADER_STAGE_COMPUTE); in nv50_compute_validate_samplers()
173 BEGIN_NV04(nv50->base.pushbuf, NV50_CP(TSC_FLUSH), 1); in nv50_compute_validate_samplers()
174 PUSH_DATA (nv50->base.pushbuf, 0); in nv50_compute_validate_samplers()
178 nv50->dirty_3d |= NV50_NEW_3D_SAMPLERS; in nv50_compute_validate_samplers()
182 nv50_compute_validate_textures(struct nv50_context *nv50) in nv50_compute_validate_textures() argument
184 bool need_flush = nv50_validate_tic(nv50, NV50_SHADER_STAGE_COMPUTE); in nv50_compute_validate_textures()
186 BEGIN_NV04(nv50->base.pushbuf, NV50_CP(TIC_FLUSH), 1); in nv50_compute_validate_textures()
187 PUSH_DATA (nv50->base.pushbuf, 0); in nv50_compute_validate_textures()
191 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES); in nv50_compute_validate_textures()
[all …]
Dnv50_tex.c223 nv50_update_tic(struct nv50_context *nv50, struct nv50_tic_entry *tic, in nv50_update_tic() argument
234 nv50_screen_tic_unlock(nv50->screen, tic); in nv50_update_tic()
242 nv50_validate_tic(struct nv50_context *nv50, int s) in nv50_validate_tic() argument
244 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_validate_tic()
245 struct nouveau_bo *txc = nv50->screen->txc; in nv50_validate_tic()
250 assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS); in nv50_validate_tic()
251 for (i = 0; i < nv50->num_textures[s]; ++i) { in nv50_validate_tic()
252 struct nv50_tic_entry *tic = nv50_tic_entry(nv50->textures[s][i]); in nv50_validate_tic()
264 nv50_update_tic(nv50, tic, res); in nv50_validate_tic()
267 tic->id = nv50_screen_tic_alloc(nv50->screen, tic); in nv50_validate_tic()
[all …]
Dnv50_surface.c202 struct nv50_context *nv50 = nv50_context(pipe); in nv50_resource_copy_region() local
208 nouveau_copy_buffer(&nv50->base, in nv50_resource_copy_region()
238 nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny); in nv50_resource_copy_region()
257 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD); in nv50_resource_copy_region()
258 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR); in nv50_resource_copy_region()
259 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx); in nv50_resource_copy_region()
260 nouveau_pushbuf_validate(nv50->base.pushbuf); in nv50_resource_copy_region()
263 ret = nv50_2d_texture_do_copy(nv50->base.pushbuf, in nv50_resource_copy_region()
272 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D); in nv50_resource_copy_region()
283 struct nv50_context *nv50 = nv50_context(pipe); in nv50_clear_render_target() local
[all …]
Dnv50_query_hw_sm.c146 nv50_hw_sm_query_get_cfg(struct nv50_context *nv50, struct nv50_hw_query *hq) in nv50_hw_sm_query_get_cfg() argument
153 nv50_hw_sm_destroy_query(struct nv50_context *nv50, struct nv50_hw_query *hq) in nv50_hw_sm_destroy_query() argument
156 nv50_hw_query_allocate(nv50, q, 0); in nv50_hw_sm_destroy_query()
162 nv50_hw_sm_begin_query(struct nv50_context *nv50, struct nv50_hw_query *hq) in nv50_hw_sm_begin_query() argument
164 struct nv50_screen *screen = nv50->screen; in nv50_hw_sm_begin_query()
165 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_hw_sm_begin_query()
171 cfg = nv50_hw_sm_query_get_cfg(nv50, hq); in nv50_hw_sm_begin_query()
215 nv50_hw_sm_end_query(struct nv50_context *nv50, struct nv50_hw_query *hq) in nv50_hw_sm_end_query() argument
217 struct nv50_screen *screen = nv50->screen; in nv50_hw_sm_end_query()
218 struct pipe_context *pipe = &nv50->base.pipe; in nv50_hw_sm_end_query()
[all …]
Dnv50_query_hw.c42 nv50_hw_query_allocate(struct nv50_context *nv50, struct nv50_query *q, in nv50_hw_query_allocate() argument
45 struct nv50_screen *screen = nv50->screen; in nv50_hw_query_allocate()
68 nv50_hw_query_allocate(nv50, q, 0); in nv50_hw_query_allocate()
108 nv50_hw_destroy_query(struct nv50_context *nv50, struct nv50_query *q) in nv50_hw_destroy_query() argument
113 hq->funcs->destroy_query(nv50, hq); in nv50_hw_destroy_query()
117 nv50_hw_query_allocate(nv50, q, 0); in nv50_hw_destroy_query()
123 nv50_hw_begin_query(struct nv50_context *nv50, struct nv50_query *q) in nv50_hw_begin_query() argument
125 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_hw_begin_query()
129 return hq->funcs->begin_query(nv50, hq); in nv50_hw_begin_query()
139 nv50_hw_query_allocate(nv50, q, NV50_HW_QUERY_ALLOC_SPACE); in nv50_hw_begin_query()
[all …]
Dnv50_query_hw_metric.c59 nv50_hw_metric_query_get_cfg(struct nv50_context *nv50, in nv50_hw_metric_query_get_cfg() argument
67 nv50_hw_metric_destroy_query(struct nv50_context *nv50, in nv50_hw_metric_destroy_query() argument
75 hmq->queries[i]->funcs->destroy_query(nv50, hmq->queries[i]); in nv50_hw_metric_destroy_query()
80 nv50_hw_metric_begin_query(struct nv50_context *nv50, struct nv50_hw_query *hq) in nv50_hw_metric_begin_query() argument
87 ret = hmq->queries[i]->funcs->begin_query(nv50, hmq->queries[i]); in nv50_hw_metric_begin_query()
95 nv50_hw_metric_end_query(struct nv50_context *nv50, struct nv50_hw_query *hq) in nv50_hw_metric_end_query() argument
101 hmq->queries[i]->funcs->end_query(nv50, hmq->queries[i]); in nv50_hw_metric_end_query()
122 nv50_hw_metric_get_query_result(struct nv50_context *nv50, in nv50_hw_metric_get_query_result() argument
133 ret = hmq->queries[i]->funcs->get_query_result(nv50, hmq->queries[i], in nv50_hw_metric_get_query_result()
152 nv50_hw_metric_create_query(struct nv50_context *nv50, unsigned type) in nv50_hw_metric_create_query() argument
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Dnv50_push.c241 nv50_push_vbo(struct nv50_context *nv50, const struct pipe_draw_info *info, in nv50_push_vbo() argument
251 ctx.push = nv50->base.pushbuf; in nv50_push_vbo()
252 ctx.translate = nv50->vertex->translate; in nv50_push_vbo()
254 ctx.need_vertex_id = nv50->screen->base.class_3d >= NV84_3D_CLASS && in nv50_push_vbo()
255 nv50->vertprog->vp.need_vertex_id && (nv50->vertex->num_elements < 32); in nv50_push_vbo()
261 ctx.need_vertex_id ? 1 : nv50->vertex->packet_vertex_limit; in nv50_push_vbo()
262 ctx.vertex_words = nv50->vertex->vertex_size; in nv50_push_vbo()
264 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS); in nv50_push_vbo()
265 for (i = 0; i < nv50->num_vtxbufs; ++i) { in nv50_push_vbo()
266 const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[i]; in nv50_push_vbo()
[all …]
Dnv50_query.c36 struct nv50_context *nv50 = nv50_context(pipe); in nv50_create_query() local
39 q = nv50_hw_create_query(nv50, type, index); in nv50_create_query()
78 struct nv50_context *nv50 = nv50_context(pipe); in nv50_render_condition() local
79 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_render_condition()
116 nv50->cond_query = pq; in nv50_render_condition()
117 nv50->cond_cond = condition; in nv50_render_condition()
118 nv50->cond_condmode = cond; in nv50_render_condition()
119 nv50->cond_mode = mode; in nv50_render_condition()
152 nv50_init_query_functions(struct nv50_context *nv50) in nv50_init_query_functions() argument
154 struct pipe_context *pipe = &nv50->base.pipe; in nv50_init_query_functions()
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Dnv50_transfer.c58 nv50_2d_transfer_rect(struct nv50_context *nv50, in nv50_2d_transfer_rect() argument
63 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_2d_transfer_rect()
64 struct nouveau_bufctx *bctx = nv50->bufctx; in nv50_2d_transfer_rect()
164 nv50_m2mf_transfer_rect(struct nv50_context *nv50, in nv50_m2mf_transfer_rect() argument
169 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_m2mf_transfer_rect()
170 struct nouveau_bufctx *bctx = nv50->bufctx; in nv50_m2mf_transfer_rect()
193 nv50_2d_transfer_rect(nv50, dst, src, nblocksx, nblocksy); in nv50_m2mf_transfer_rect()
279 struct nv50_context *nv50 = nv50_context(&nv->pipe); in nv50_sifc_linear_u8() local
280 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_sifc_linear_u8()
285 nouveau_bufctx_refn(nv50->bufctx, 0, dst, domain | NOUVEAU_BO_WR); in nv50_sifc_linear_u8()
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Dnv50_program.c469 nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog) in nv50_program_upload_code() argument
477 case PIPE_SHADER_VERTEX: heap = nv50->screen->vp_code_heap; break; in nv50_program_upload_code()
478 case PIPE_SHADER_GEOMETRY: heap = nv50->screen->gp_code_heap; break; in nv50_program_upload_code()
479 case PIPE_SHADER_FRAGMENT: heap = nv50->screen->fp_code_heap; break; in nv50_program_upload_code()
480 case PIPE_SHADER_COMPUTE: heap = nv50->screen->fp_code_heap; break; in nv50_program_upload_code()
512 ret = nv50_tls_realloc(nv50->screen, prog->tls_space); in nv50_program_upload_code()
518 nv50->state.new_tls_space = true; in nv50_program_upload_code()
529 nv50_sifc_linear_u8(&nv50->base, nv50->screen->code, in nv50_program_upload_code()
533 BEGIN_NV04(nv50->base.pushbuf, NV50_3D(CODE_CB_FLUSH), 1); in nv50_program_upload_code()
534 PUSH_DATA (nv50->base.pushbuf, 0); in nv50_program_upload_code()
[all …]
/third_party/mesa3d/src/gallium/drivers/nouveau/
Dmeson.build78 'nv50/g80_defs.xml.h',
79 'nv50/g80_texture.xml.h',
80 'nv50/nv50_2d.xml.h',
81 'nv50/nv50_3ddefs.xml.h',
82 'nv50/nv50_3d.xml.h',
83 'nv50/nv50_blit.h',
84 'nv50/nv50_compute.c',
85 'nv50/nv50_compute.xml.h',
86 'nv50/nv50_context.c',
87 'nv50/nv50_context.h',
[all …]
/third_party/mesa3d/docs/relnotes/
D10.2.rst29 - GL_ARB_buffer_storage on i965, nv30, nv50, nvc0, r300, r600, and
32 - GL_ARB_sample_shading on nv50 (GT21x only), nvc0
36 - GL_ARB_texture_cube_map_array on nv50 (GT21x only)
37 - GL_ARB_texture_gather on nv50 (GT21x only), nvc0
38 - GL_ARB_texture_query_lod on nv50 (GT21x only), nvc0
40 - GL_ARB_vertex_type_10f_11f_11f_rev on nv50, nvc0, radeonsi
41 - GL_ARB_viewport_array on nv50, r600
D11.0.8.rst96 - nv50/ir: deal with loops with no breaks
97 - nv50/ir: the mad source might not have a defining instruction
98 - nv50/ir: fix instruction permutation logic
99 - nv50/ir: don't forget to mark flagsDef on cvt in txb lowering
100 - nv50/ir: fix DCE to not generate 96-bit loads
101 - nv50/ir: avoid looking at uninitialized srcMods entries
105 - nv50/ir: fix cutoff for using r63 vs r127 when replacing zero
106 - nv50/ir: can't have predication and immediates
157 - nv50,nvc0: fix use-after-free when vertex buffers are unbound
D11.1.1.rst88 - nv50/ir: can't have predication and immediates
93 - nv50/ir: float(s32 & 0xff) = float(u8), not s8
94 - nv50,nvc0: make sure there's pushbuf space and that we ref the bo
96 - nv50,nvc0: fix crash when increasing bsp bo size for h264
151 - nv50,nvc0: fix use-after-free when vertex buffers are unbound
162 - nv50,nvc0: free memory allocated by performance metrics
163 - nv50: free memory allocated by the prog which reads MP perf counters
D10.3.5.rst56 - nv50/ir: set neg modifiers on min/max args
57 - nv50,nvc0: actually check constbufs for invalidation
58 - nv50,nvc0: buffer resources can be bound as other things down the
D10.5.3.rst71 - nv50/ir: take postFactor into account when doing peephole
73 - nv50/ir/gk110: fix offset flag position for TXD opcode
76 - nv50: allocate more offset space for occlusion queries
77 - nv50,nvc0: limit the y-tiling of 3d textures to the first level's
D10.5.6.rst39 [nv50] HW state is not reset correctly when using a new GL context
77 - nv50/ir: only propagate saturate up if some actual folding took place
78 - nv50: keep track of PGRAPH state in nv50_screen
82 - nv50/ir: only enable mul saturate on G200+
D10.1.4.rst63 - nv50/ir: make sure to reverse cond codes on all the OP_SET variants
64 - nv50: fix setting of texture ms info to be per-stage
65 - nv50/ir: fix integer mul lowering for u32 x u32 -> high u32
/third_party/mesa3d/docs/
Dfeatures.txt39 GL 3.0, GLSL 1.30 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, sw…
72 GL 3.1, GLSL 1.40 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, sw…
85 GL 3.2, GLSL 1.50 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, sw…
100 GL 3.3, GLSL 3.30 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, vi…
116 …GL_ARB_draw_buffers_blend DONE (freedreno, i965/gen6+, nv50, softpipe,…
132 …GL_ARB_sample_shading DONE (freedreno/a6xx, i965/gen6+, nv50, panf…
133 …GL_ARB_shader_subroutine DONE (freedreno, i965/gen6+, nv50, softpipe,…
136 …GL_ARB_texture_cube_map_array DONE (freedreno/a4xx+, i965/gen6+, nv50, sof…
137 …GL_ARB_texture_gather DONE (freedreno, i965/gen6+, nv50, softpipe,…
138 …GL_ARB_texture_query_lod DONE (freedreno, i965, nv50, softpipe, swr, …
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/third_party/libdrm/nouveau/
Dabi16.c297 bo->config.nv50.memtype = (info->tile_flags & 0x07f00) >> 8 | in abi16_bo_info()
299 bo->config.nv50.tile_mode = info->tile_mode << 4; in abi16_bo_info()
342 info->tile_flags = (config->nv50.memtype & 0x07f) << 8 | in abi16_bo_init()
343 (config->nv50.memtype & 0x180) << 9; in abi16_bo_init()
344 info->tile_mode = config->nv50.tile_mode >> 4; in abi16_bo_init()

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