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Searched refs:output_patch_size (Results 1 – 3 of 3) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dradv_shader.h563 unsigned output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16; in calculate_tess_lds_size() local
567 unsigned lds_size = output_patch0_offset + output_patch_size * tcs_num_patches; in calculate_tess_lds_size()
590 uint32_t output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16; in get_tcs_num_patches() local
610 if (input_patch_size + output_patch_size) in get_tcs_num_patches()
611 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size)); in get_tcs_num_patches()
613 if (output_patch_size) in get_tcs_num_patches()
614 num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size); in get_tcs_num_patches()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.cpp577 unsigned output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16; in si_emit_derived_tess_state() local
588 lds_per_patch = input_patch_size + output_patch_size; in si_emit_derived_tess_state()
591 lds_per_patch = MAX2(input_patch_size, output_patch_size); in si_emit_derived_tess_state()
616 MIN2(*num_patches, (sctx->screen->tess_offchip_block_dw_size * 4) / output_patch_size); in si_emit_derived_tess_state()
670 assert(((output_patch_size / 4) & ~0x1fff) == 0); in si_emit_derived_tess_state()
684 unsigned tcs_out_layout = (output_patch_size / 4) | (num_tcs_input_cp << 13) | ring_va; in si_emit_derived_tess_state()
/third_party/mesa3d/src/gallium/drivers/r600/
Devergreen_state.c4541 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size; in evergreen_setup_tess_constants() local
4586 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16; in evergreen_setup_tess_constants()
4591 lds_size = output_patch0_offset + output_patch_size * *num_patches; in evergreen_setup_tess_constants()
4598 values[4] = output_patch_size; in evergreen_setup_tess_constants()