Searched refs:ra_alloc_contig_reg_class (Results 1 – 9 of 9) sorted by relevance
| /third_party/mesa3d/src/util/ |
| D | register_allocate_test.cpp | 131 struct ra_class *reg32low = ra_alloc_contig_reg_class(regs, 1); in TEST_F()
136 struct ra_class *reg64low = ra_alloc_contig_reg_class(regs, 2); in TEST_F()
141 struct ra_class *reg96 = ra_alloc_contig_reg_class(regs, 3); in TEST_F()
154 struct ra_class *low = ra_alloc_contig_reg_class(regs, 1); in TEST_F()
158 struct ra_class *high = ra_alloc_contig_reg_class(regs, 1); in TEST_F()
175 struct ra_class *c1 = ra_alloc_contig_reg_class(regs, 1); in TEST_F()
179 struct ra_class *c2 = ra_alloc_contig_reg_class(regs, 2); in TEST_F()
183 struct ra_class *c4 = ra_alloc_contig_reg_class(regs, 4); in TEST_F()
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| D | register_allocate.h | 57 struct ra_class *ra_alloc_contig_reg_class(struct ra_regs *regs, int contig_len);
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| D | register_allocate.c | 245 ra_alloc_contig_reg_class(struct ra_regs *regs, int contig_len) in ra_alloc_contig_reg_class() function
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_register_allocate.c | 125 vc4->reg_class_any[i] = ra_alloc_contig_reg_class(vc4->regs, 1); in vc4_alloc_reg_set()
126 vc4->reg_class_a_or_b[i] = ra_alloc_contig_reg_class(vc4->regs, 1); in vc4_alloc_reg_set()
127 vc4->reg_class_a_or_b_or_acc[i] = ra_alloc_contig_reg_class(vc4->regs, 1); in vc4_alloc_reg_set()
128 vc4->reg_class_r4_or_a[i] = ra_alloc_contig_reg_class(vc4->regs, 1); in vc4_alloc_reg_set()
129 vc4->reg_class_a[i] = ra_alloc_contig_reg_class(vc4->regs, 1); in vc4_alloc_reg_set()
131 vc4->reg_class_r0_r3 = ra_alloc_contig_reg_class(vc4->regs, 1); in vc4_alloc_reg_set()
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| /third_party/mesa3d/src/broadcom/compiler/ |
| D | vir_register_allocate.c | 504 ra_alloc_contig_reg_class(compiler->regs, 1); in vir_init_reg_sets()
506 ra_alloc_contig_reg_class(compiler->regs, 1); in vir_init_reg_sets()
508 ra_alloc_contig_reg_class(compiler->regs, 1); in vir_init_reg_sets()
510 ra_alloc_contig_reg_class(compiler->regs, 1); in vir_init_reg_sets()
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| /third_party/mesa3d/src/gallium/drivers/lima/ir/pp/ |
| D | regalloc.c | 61 classes[i] = ra_alloc_contig_reg_class(ret, i + 1); in ppir_regalloc_init()
71 classes[i] = ra_alloc_contig_reg_class(ret, i - ppir_ra_reg_class_head_vec1 + 1); in ppir_regalloc_init()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_fs_reg_allocate.cpp | 131 classes[i] = ra_alloc_contig_reg_class(regs, class_sizes[i]); in brw_alloc_reg_set()
158 aligned_bary_class = ra_alloc_contig_reg_class(regs, contig_len); in brw_alloc_reg_set()
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| D | brw_vec4_reg_allocate.cpp | 121 ra_alloc_contig_reg_class(compiler->vec4_reg_set.regs, class_sizes[i]); in brw_vec4_alloc_reg_set()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.2.0.rst | 2029 - vc4: Use the ra_alloc_contig_reg_class() function to speed up RA.
2030 - v3d: Use the ra_alloc_contig_reg_class() function to speed up RA.
2031 - intel/fs: Use ra_alloc_contig_reg_class() to speed up RA.
2032 - intel/vec4: Use ra_alloc_contig_reg_class() to reduce RA overhead.
2033 - lima: Use ra_alloc_contig_reg_class().
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