Home
last modified time | relevance | path

Searched refs:raddr_b (Results 1 – 11 of 11) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/vc4/kernel/
Dvc4_validate_shaders.c118 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); in raddr_add_a_to_live_reg_index() local
123 return 32 + raddr_b; in raddr_add_a_to_live_reg_index()
188 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); in check_tmu_write() local
236 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) { in check_tmu_write()
244 raddr_b == QPU_R_UNIF)) { in check_tmu_write()
310 u32 raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); in validate_uniform_address_write() local
364 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) { in validate_uniform_address_write()
479 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); in track_live_clamps() local
518 if (sig != QPU_SIG_SMALL_IMM || raddr_b != 0 || in track_live_clamps()
532 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF && in track_live_clamps()
[all …]
/third_party/mesa3d/src/broadcom/compiler/
Dqpu_schedule.c163 state->last_rf[n->inst->qpu.raddr_b], n); in process_mux_deps()
614 !inst->sig.small_imm && (inst->raddr_b == waddr)) in qpu_instruction_uses_rf()
757 raddrs_used |= (1ll << a->raddr_b); in qpu_raddrs_used()
761 raddrs_used |= (1ll << b->raddr_b); in qpu_raddrs_used()
787 if (add_instr->raddr_b != mul_instr->raddr_b) in qpu_merge_raddrs()
791 result->raddr_b = add_instr->sig.small_imm ? in qpu_merge_raddrs()
792 add_instr->raddr_b : mul_instr->raddr_b; in qpu_merge_raddrs()
804 raddr_a == add_instr->raddr_b) { in qpu_merge_raddrs()
813 raddr_a == mul_instr->raddr_b) { in qpu_merge_raddrs()
825 int raddr_b = ffsll(raddrs_used) - 1; in qpu_merge_raddrs() local
[all …]
Dvir_to_qpu.c123 src.index == instr->raddr_b); in set_src()
125 instr->raddr_b = src.index; in set_src()
162 raddr = qinst->qpu.raddr_b; in is_no_op_mov()
Dvir_opt_small_immediates.c93 inst->qpu.raddr_b = packed; in vir_opt_small_immediates()
Dvir_dump.c173 inst->qpu.raddr_b, in vir_print_reg()
177 int8_t *p = (int8_t *)&inst->qpu.raddr_b; in vir_print_reg()
Dvir_opt_constant_alu.c126 inst->qpu.raddr_b, in try_opt_constant_alu()
/third_party/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu_schedule.c331 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); in calculate_deps() local
342 process_raddr_deps(state, n, raddr_b, false); in calculate_deps()
457 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); in reads_too_soon_after_write() local
476 raddr_b < 32 && in reads_too_soon_after_write()
477 scoreboard->last_waddr_b == raddr_b)) { in reads_too_soon_after_write()
Dvc4_qpu.c291 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B); in qpu_num_sf_accesses() local
302 if (raddr_b == QPU_R_MUTEX_ACQUIRE && in qpu_num_sf_accesses()
/third_party/mesa3d/src/broadcom/qpu/
Dqpu_disasm.c69 instr->raddr_b, in v3d_qpu_disasm_raddr()
78 append(disasm, "rf%d", instr->raddr_b); in v3d_qpu_disasm_raddr()
Dqpu_instr.h383 uint8_t raddr_b; member
Dqpu_pack.c1338 instr->raddr_b = QPU_GET_FIELD(packed_instr, V3D_QPU_RADDR_B); in v3d_qpu_instr_unpack_alu()
1425 *packed_instr |= QPU_SET_FIELD(instr->raddr_b, V3D_QPU_RADDR_B); in v3d_qpu_instr_pack_alu()