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Searched refs:radeon_set_context_reg (Results 1 – 19 of 19) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/r600/
Dcayman_msaa.c149 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0); in cayman_emit_msaa_sample_locs()
150 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0); in cayman_emit_msaa_sample_locs()
151 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0); in cayman_emit_msaa_sample_locs()
152 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0); in cayman_emit_msaa_sample_locs()
155 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]); in cayman_emit_msaa_sample_locs()
156 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]); in cayman_emit_msaa_sample_locs()
157 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]); in cayman_emit_msaa_sample_locs()
158 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]); in cayman_emit_msaa_sample_locs()
161 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]); in cayman_emit_msaa_sample_locs()
162 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]); in cayman_emit_msaa_sample_locs()
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Dr600_streamout.c284 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0); in r600_emit_streamout_end()
318 radeon_set_context_reg(&rctx->gfx.cs, strmout_buffer_reg, strmout_buffer_val); in r600_emit_streamout_enable()
319 radeon_set_context_reg(&rctx->gfx.cs, strmout_config_reg, strmout_config_val); in r600_emit_streamout_enable()
Dr600_state.c286 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, in r600_emit_polygon_offset()
1385 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base); in r600_emit_framebuffer_state()
1398 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask); in r600_emit_framebuffer_state()
1411 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask); in r600_emit_framebuffer_state()
1470 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit); in r600_emit_framebuffer_state()
1476 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID)); in r600_emit_framebuffer_state()
1494 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1); in r600_emit_framebuffer_state()
1499 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, in r600_emit_framebuffer_state()
1535 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control); in r600_emit_cb_misc_state()
1545 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, in r600_emit_cb_misc_state()
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Devergreen_state.c998 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, in evergreen_emit_config_state()
1696 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, in evergreen_emit_msaa_state()
1704 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, in evergreen_emit_msaa_state()
1782 …radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_addres… in evergreen_emit_image_state()
1860 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, in evergreen_emit_framebuffer_state()
1911 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, in evergreen_emit_framebuffer_state()
1918 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); in evergreen_emit_framebuffer_state()
1920 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0); in evergreen_emit_framebuffer_state()
1933 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); in evergreen_emit_framebuffer_state()
2015 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, in evergreen_emit_polygon_offset()
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Dr600_cs.h153 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg() function
Dr600_state_common.c93 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL, in r600_emit_alphatest_state()
96 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref); in r600_emit_alphatest_state()
268 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en); in r600_emit_vgt_state()
1741 radeon_set_context_reg(cs, item_size_reg, itemsize); in r600_setup_scratch_area_for_shader()
2046 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, in r600_emit_clip_misc_state()
2050 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, in r600_emit_clip_misc_state()
2056 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, in r600_emit_clip_misc_state()
2080 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE, in r600_emit_rasterizer_prim_state()
2295 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM, in r600_draw_vbo()
2325 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl); in r600_draw_vbo()
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Dr600_hw_context.c289 radeon_set_context_reg(cs, R_028350_SX_MISC, 0); in r600_context_gfx_flush()
Dr600_pipe.h1015 radeon_set_context_reg(cs, reg, value); in radeon_set_context_reg_flag()
/third_party/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c57 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]); in si_write_harvested_raster_configs()
71 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); in si_write_harvested_raster_configs()
173 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config); in si_set_raster_config()
175 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); in si_set_raster_config()
201 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); in si_emit_graphics()
203 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); in si_emit_graphics()
207 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES); in si_emit_graphics()
208 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40); in si_emit_graphics()
212 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2); in si_emit_graphics()
213 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); in si_emit_graphics()
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Dradv_pipeline.c4281 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control); in radv_pipeline_generate_depth_stencil_state()
4295 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask); in radv_pipeline_generate_blend_state()
4303 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format); in radv_pipeline_generate_blend_state()
4305 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask); in radv_pipeline_generate_blend_state()
4337 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, in radv_pipeline_generate_raster_state()
4352 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa); in radv_pipeline_generate_multisample_state()
4353 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config); in radv_pipeline_generate_multisample_state()
4364 radeon_set_context_reg( in radv_pipeline_generate_multisample_state()
4393 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en); in radv_pipeline_generate_vgt_gs_mode()
4394 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode); in radv_pipeline_generate_vgt_gs_mode()
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Dradv_cmd_buffer.c967 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, in radv_emit_sample_locations()
969 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, in radv_emit_sample_locations()
971 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, in radv_emit_sample_locations()
973 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, in radv_emit_sample_locations()
977 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, in radv_emit_sample_locations()
979 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, in radv_emit_sample_locations()
981 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, in radv_emit_sample_locations()
983 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, in radv_emit_sample_locations()
985 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, in radv_emit_sample_locations()
987 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, in radv_emit_sample_locations()
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Dradv_cs.h70 radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg() function
Dradv_device.c3646 radeon_set_context_reg( in radv_emit_graphics_scratch()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_msaa.c157 radeon_set_context_reg(R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs); in si_emit_max_4_sample_locs()
158 radeon_set_context_reg(R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs); in si_emit_max_4_sample_locs()
159 radeon_set_context_reg(R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs); in si_emit_max_4_sample_locs()
160 radeon_set_context_reg(R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs); in si_emit_max_4_sample_locs()
Dsi_build_pm4.h95 #define radeon_set_context_reg(reg, value) do { \ macro
160 radeon_set_context_reg(offset, __value); \
Dsi_state.c3059 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, in si_emit_framebuffer_state()
3154 radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_color_base >> 32); in si_emit_framebuffer_state()
3155 radeon_set_context_reg(R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4, in si_emit_framebuffer_state()
3157 radeon_set_context_reg(R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4, in si_emit_framebuffer_state()
3159 radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32); in si_emit_framebuffer_state()
3160 radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb_color_attrib2); in si_emit_framebuffer_state()
3161 radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3); in si_emit_framebuffer_state()
3200 radeon_set_context_reg(R_0287A0_CB_MRT0_EPITCH + i * 4, in si_emit_framebuffer_state()
3266 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); in si_emit_framebuffer_state()
3302 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); in si_emit_framebuffer_state()
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Dsi_state_draw.cpp768 radeon_set_context_reg(R_028B58_VGT_LS_HS_CONFIG, ls_hs_config); in si_emit_derived_tess_state()
1081 radeon_set_context_reg(R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim); in si_emit_rasterizer_prim_state()
1187 radeon_set_context_reg(R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); in si_emit_ia_multi_vgt_param()
1284 radeon_set_context_reg(R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart); in si_emit_draw_registers()
1289 radeon_set_context_reg(R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, restart_index); in si_emit_draw_registers()
1331 radeon_set_context_reg(R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw); in si_emit_draw_packets()
Dsi_state_streamout.c396 radeon_set_context_reg(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 0); in si_emit_streamout_end()
Dsi_state_shaders.c4036 radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size); in si_emit_scratch_state()