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Searched refs:read_domains (Results 1 – 25 of 26) sorted by relevance

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/third_party/libdrm/radeon/
Dradeon_cs_space.c44 uint32_t read_domains, write_domain; in radeon_cs_setup_bo() local
49 read_domains = sc->read_domains; in radeon_cs_setup_bo()
54 bo->space_accounted = sc->new_accounted = (read_domains << 16) | write_domain; in radeon_cs_setup_bo()
63 if (read_domains && ((read_domains << 16) == bo->space_accounted)) { in radeon_cs_setup_bo()
77 sc->new_accounted = read_domains << 16; in radeon_cs_setup_bo()
95 } else if (read_domains & old_write) { in radeon_cs_setup_bo()
101 if (read_domains != old_read) in radeon_cs_setup_bo()
102 … fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); in radeon_cs_setup_bo()
167 uint32_t read_domains, uint32_t write_domain) in radeon_cs_space_add_persistent_bo() argument
174 csi->bos[i].read_domains == read_domains && in radeon_cs_space_add_persistent_bo()
[all …]
Dradeon_cs.h98 uint32_t read_domains,
112 uint32_t read_domains,
Dradeon_bo_gem.h42 int radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain);
Dradeon_bo_gem.c344 radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain) in radeon_gem_set_domain() argument
351 args.read_domains = read_domains; in radeon_gem_set_domain()
Dradeon_cs_int.h7 uint32_t read_domains; member
/third_party/mesa3d/src/mesa/drivers/dri/i915/
Dintel_batchbuffer.h43 uint32_t read_domains,
48 uint32_t read_domains,
139 #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \ argument
141 read_domains, write_domain, delta); \
143 #define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do { \ argument
145 read_domains, write_domain, delta); \
Dintel_batchbuffer.c197 uint32_t read_domains, uint32_t write_domain, in intel_batchbuffer_emit_reloc() argument
204 read_domains, write_domain); in intel_batchbuffer_emit_reloc()
221 uint32_t read_domains, in intel_batchbuffer_emit_reloc_fenced() argument
229 read_domains, write_domain); in intel_batchbuffer_emit_reloc_fenced()
/third_party/libdrm/intel/
Dintel_bufmgr.c201 uint32_t read_domains, uint32_t write_domain) in drm_intel_bo_emit_reloc() argument
205 read_domains, write_domain); in drm_intel_bo_emit_reloc()
212 uint32_t read_domains, uint32_t write_domain) in drm_intel_bo_emit_reloc_fence() argument
216 read_domains, write_domain); in drm_intel_bo_emit_reloc_fence()
Dintel_bufmgr_priv.h190 uint32_t read_domains, uint32_t write_domain);
194 uint32_t read_domains,
Dintel_bufmgr_fake.c83 uint32_t read_domains; member
200 uint32_t read_domains; member
1252 uint32_t read_domains, uint32_t write_domain) in drm_intel_fake_emit_reloc() argument
1286 r->read_domains = read_domains; in drm_intel_fake_emit_reloc()
1323 target_fake->read_domains |= r->read_domains; in drm_intel_fake_calculate_domains()
1408 bo_fake->read_domains = 0; in drm_intel_bo_fake_post_submit()
1442 batch_fake->read_domains = I915_GEM_DOMAIN_COMMAND; in drm_intel_fake_bo_exec()
Dintel_bufmgr.h153 uint32_t read_domains, uint32_t write_domain);
157 uint32_t read_domains, uint32_t write_domain);
Dintel_bufmgr_gem.c1494 set_domain.read_domains = I915_GEM_DOMAIN_CPU; in drm_intel_gem_bo_map()
1608 set_domain.read_domains = I915_GEM_DOMAIN_GTT; in drm_intel_gem_bo_map_gtt()
1900 set_domain.read_domains = I915_GEM_DOMAIN_GTT; in drm_intel_gem_bo_start_gtt_access()
1908 set_domain.read_domains, set_domain.write_domain, in drm_intel_gem_bo_start_gtt_access()
1968 uint32_t read_domains, uint32_t write_domain, in do_bo_emit_reloc() argument
2034 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains; in do_bo_emit_reloc()
2094 uint32_t read_domains, uint32_t write_domain) in drm_intel_gem_bo_emit_reloc() argument
2103 read_domains, write_domain, in drm_intel_gem_bo_emit_reloc()
2111 uint32_t read_domains, uint32_t write_domain) in drm_intel_gem_bo_emit_reloc_fence() argument
2114 read_domains, write_domain, true); in drm_intel_gem_bo_emit_reloc_fence()
/third_party/libdrm/nouveau/
Dpushbuf.c192 kref->read_domains |= domains_rd; in pushbuf_kref()
203 kref->read_domains = domains_rd; in pushbuf_kref()
279 kref->read_domains, kref->write_domains); in pushbuf_dump()
380 if (kref->read_domains) in pushbuf_submit()
761 if (kref->read_domains) in nouveau_pushbuf_refd()
/third_party/mesa3d/src/intel/vulkan/
Danv_gem.c200 uint32_t read_domains, uint32_t write_domain) in anv_gem_set_domain() argument
204 .read_domains = read_domains, in anv_gem_set_domain()
Danv_gem_stubs.c129 uint32_t read_domains, uint32_t write_domain) in anv_gem_set_domain() argument
Danv_batch_chain.c229 entry->read_domains = 0; in anv_reloc_list_add()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_cs.c303 reloc->read_domains = 0; in radeon_lookup_or_add_real_buffer()
394 added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain); in radeon_drm_cs_add_buffer()
395 reloc->read_domains |= rd; in radeon_drm_cs_add_buffer()
770 if ((usage & RADEON_USAGE_READ) && cs->csc->relocs[index].read_domains) in radeon_bo_is_referenced()
/third_party/libdrm/include/drm/
Dnouveau_drm.h136 __u32 read_domains; member
Dradeon_drm.h879 __u32 read_domains; member
979 __u32 read_domains; member
Di915_drm.h769 __u32 read_domains; member
813 __u32 read_domains; member
/third_party/mesa3d/include/drm-uapi/
Di915_drm.h963 __u32 read_domains; member
1012 __u32 read_domains; member
/third_party/mesa3d/src/gallium/drivers/crocus/
Dcrocus_bufmgr.c377 .read_domains = I915_GEM_DOMAIN_CPU, in alloc_fresh_bo()
493 .read_domains = I915_GEM_DOMAIN_CPU, in crocus_bo_create_userptr()
/third_party/mesa3d/src/gallium/drivers/iris/
Diris_bufmgr.c973 .read_domains = I915_GEM_DOMAIN_CPU, in alloc_fresh_bo()
1115 .read_domains = I915_GEM_DOMAIN_CPU, in iris_bo_create_userptr()
/third_party/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_bufmgr.c667 .read_domains = I915_GEM_DOMAIN_CPU, in bo_alloc_internal()
Dbrw_screen.c2040 .read_domains = I915_GEM_DOMAIN_INSTRUCTION, in brw_detect_pipelined_register()

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