| /third_party/openssl/crypto/aria/ |
| D | aria.c | 474 register uint32_t reg0, reg1, reg2, reg3; in aria_encrypt() local
489 reg0 = GET_U32_BE(in, 0); in aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
511 reg0 = rk->u[0] ^ MAKE_U32( in aria_encrypt()
[all …]
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| /third_party/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_fragshader.c | 48 GLuint reg0 = 0; in r200SetFragShaderArg() local
76 reg0 |= (((index - GL_REG_0_ATI)*2) + 10 + useOddSrc) << (5*argPos); in r200SetFragShaderArg()
79 reg0 |= (R200_TXC_ARG_A_TFACTOR_COLOR + useOddSrc) << (5*argPos); in r200SetFragShaderArg()
84 reg0 |= (R200_TXC_ARG_A_TFACTOR1_COLOR + useOddSrc) << (5*argPos); in r200SetFragShaderArg()
89 reg0 |= (R200_TXC_ARG_A_DIFFUSE_COLOR + useOddSrc) << (5*argPos); in r200SetFragShaderArg()
92 reg0 |= (R200_TXC_ARG_A_SPECULAR_COLOR + useOddSrc) << (5*argPos); in r200SetFragShaderArg()
96 reg0 |= R200_TXC_COMP_ARG_A << (4*argPos); in r200SetFragShaderArg()
100 reg0 ^= R200_TXC_COMP_ARG_A << (4*argPos); in r200SetFragShaderArg()
102 reg0 |= R200_TXC_BIAS_ARG_A << (4*argPos); in r200SetFragShaderArg()
104 reg0 |= R200_TXC_SCALE_ARG_A << (4*argPos); in r200SetFragShaderArg()
[all …]
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| /third_party/ffmpeg/libavcodec/mips/ |
| D | vp9_idct_msa.c | 67 #define VP9_DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \ argument
75 ILVRL_H2_SW((-reg1), reg0, s1_m, s0_m); \
76 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
967 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
985 VP9_DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8); in vp9_idct16_1d_columns_addblk_msa()
987 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_msa()
989 reg0 = reg2 - loc1; in vp9_idct16_1d_columns_addblk_msa()
1018 loc0 = reg0 + loc1; in vp9_idct16_1d_columns_addblk_msa()
1019 loc1 = reg0 - loc1; in vp9_idct16_1d_columns_addblk_msa()
[all …]
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| D | h264pred_msa.c | 217 v4i32 reg0, reg1, reg2, reg3; in intra_predict_plane_16x16_msa() local
259 reg0 = vec7; in intra_predict_plane_16x16_msa()
262 reg0 += vec4; in intra_predict_plane_16x16_msa()
264 reg1 = reg0 + vec6; in intra_predict_plane_16x16_msa()
271 SRA_4V(reg0, reg1, reg2, reg3, 5); in intra_predict_plane_16x16_msa()
273 PCKEV_H2_SH(reg1, reg0, reg3, reg2, vec11, vec12); in intra_predict_plane_16x16_msa()
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| /third_party/pixman/pixman/ |
| D | pixman-arm-simd-asm.h | 114 .macro pixldst op, cond=al, numbytes, reg0, reg1, reg2, reg3, base, unaligned=0
117 op&r&cond WK®0, [base], #4
122 op&m&cond&ia base!, {WK®0,WK®1,WK®2,WK®3}
126 op&r&cond WK®0, [base], #4
129 op&m&cond&ia base!, {WK®0,WK®1}
132 op&r&cond WK®0, [base], #4
134 op&r&cond&h WK®0, [base], #2
136 op&r&cond&b WK®0, [base], #1
142 .macro pixst_baseupdated cond, numbytes, reg0, reg1, reg2, reg3, base
144 stm&cond&db base, {WK®0,WK®1,WK®2,WK®3}
[all …]
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| D | pixman-arm-simd-asm.S | 452 .macro over_8888_8888_check_transparent numbytes, reg0, reg1, reg2, reg3
454 teq WK®0, #0
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | egd_tables.py | 207 reg0 = reg_dict.get(match_number.sub('0', reg.name))
208 if reg0 != None:
209 reg.fields = reg0.fields
210 reg.fields_owner = reg0
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| /third_party/mesa3d/src/panfrost/bifrost/ |
| D | disassemble.c | 59 return regs.reg0 | ((regs.reg1 & 0x1) << 5); in get_reg0()
61 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0; in get_reg0()
66 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1; in get_reg1()
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| D | bi_pack.c | 222 s.reg0 = regs.slot[0]; in bi_pack_registers()
233 s.reg0 = (regs.slot[0] & 0b11111); in bi_pack_registers()
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| D | bifrost.h | 220 unsigned reg0 : 5; member
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| /third_party/mesa3d/src/util/ |
| D | register_allocate.h | 66 unsigned int base_reg, unsigned int reg0, unsigned int reg1);
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| D | register_allocate.c | 180 unsigned int base_reg, unsigned int reg0, unsigned int reg1) in ra_add_transitive_reg_pair_conflict() argument
182 ra_add_reg_conflict(regs, reg0, base_reg); in ra_add_transitive_reg_pair_conflict()
188 ra_add_reg_conflict(regs, reg0, conflict); in ra_add_transitive_reg_pair_conflict()
189 if (conflict != reg0) in ra_add_transitive_reg_pair_conflict()
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| /third_party/ffmpeg/libavcodec/x86/ |
| D | hevc_mc.asm | 479 %define %%reg0 %5
484 %define %%reg0 m0
502 pmaddubsw %%reg0, %3 ;x1*c1+x2*c2
504 paddw %%reg0, %%reg2
511 pmaddwd %%reg0, %3
513 paddd %%reg0, %%reg2
523 psrad %%reg0, %1-8
525 packssdw %%reg0, %%reg1
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerX8664.cpp | 2168 void AssemblerX8664::arith_int(Type Ty, GPRRegister reg0, GPRRegister reg1) { in arith_int() argument
2173 emitRexRB(Ty, reg0, reg1); in arith_int()
2178 emitRegisterOperand(gprEncoding(reg0), gprEncoding(reg1)); in arith_int()
2230 void AssemblerX8664::cmp(Type Ty, GPRRegister reg0, GPRRegister reg1) { in cmp() argument
2231 arith_int<7>(Ty, reg0, reg1); in cmp()
3130 void AssemblerX8664::xchg(Type Ty, GPRRegister reg0, GPRRegister reg1) { in xchg() argument
3135 if (reg0 == RegX8664::Encoded_Reg_rax) { in xchg()
3139 emitRexB(Ty, reg0); in xchg()
3140 emitUint8(0x90 + gprEncoding(reg0)); in xchg()
3142 emitRexRB(Ty, reg0, reg1); in xchg()
[all …]
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| D | IceAssemblerX8632.h | 716 void cmp(Type Ty, GPRRegister reg0, GPRRegister reg1);
722 void test(Type Ty, GPRRegister reg0, GPRRegister reg1);
860 void xchg(Type Ty, GPRRegister reg0, GPRRegister reg1);
923 void arith_int(Type Ty, GPRRegister reg0, GPRRegister reg1);
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| D | IceAssemblerX8664.h | 711 void cmp(Type Ty, GPRRegister reg0, GPRRegister reg1);
717 void test(Type Ty, GPRRegister reg0, GPRRegister reg1);
856 void xchg(Type Ty, GPRRegister reg0, GPRRegister reg1);
919 void arith_int(Type Ty, GPRRegister reg0, GPRRegister reg1);
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| D | IceAssemblerX8632.cpp | 2050 void AssemblerX8632::arith_int(Type Ty, GPRRegister reg0, GPRRegister reg1) { in arith_int() argument
2059 emitRegisterOperand(gprEncoding(reg0), gprEncoding(reg1)); in arith_int()
2108 void AssemblerX8632::cmp(Type Ty, GPRRegister reg0, GPRRegister reg1) { in cmp() argument
2109 arith_int<7>(Ty, reg0, reg1); in cmp()
2972 void AssemblerX8632::xchg(Type Ty, GPRRegister reg0, GPRRegister reg1) { in xchg() argument
2977 if (reg0 == RegX8632::Encoded_Reg_eax) { in xchg()
2980 emitUint8(0x90 + gprEncoding(reg0)); in xchg()
2986 emitRegisterOperand(gprEncoding(reg0), gprEncoding(reg1)); in xchg()
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| /third_party/mesa3d/src/freedreno/decode/ |
| D | crashdec.c | 594 uint32_t reg0 : 18; in dump_mem_pool_chunk() member
606 dump_mem_pool_reg_write(fields.reg0, fields.data0, fields.reg0_context, in dump_mem_pool_chunk()
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| /third_party/openssl/crypto/perlasm/ |
| D | x86_64-xlate.pl | 525 reg0 => 0x50, # add 0-31 to opcode
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| /third_party/skia/third_party/externals/opengl-registry/extensions/ATI/ |
| D | ATI_text_fragment_shader.txt | 1126 ADD r0, r3, r4; # reg0 = ((spec * env map) + diff * env map)
1173 ADD r0, r3, r4; # reg0 = specular + diffuse
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| D | ATI_fragment_shader.txt | 883 // reg0 = (specular * environment map) + (diffuse * environment map)
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| /third_party/openGLES/extensions/ATI/ |
| D | ATI_text_fragment_shader.txt | 1126 ADD r0, r3, r4; # reg0 = ((spec * env map) + diff * env map)
1173 ADD r0, r3, r4; # reg0 = specular + diffuse
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| D | ATI_fragment_shader.txt | 883 // reg0 = (specular * environment map) + (diffuse * environment map)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/BinaryFormat/ |
| D | Dwarf.def | 555 HANDLE_DW_OP(0x50, reg0, 2, DWARF)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3589 def SEH_SaveRegP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;
3590 …def SEH_SaveRegP_X : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;
3593 def SEH_SaveFRegP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;
3594 …def SEH_SaveFRegP_X : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]…
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