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Searched refs:reg1 (Results 1 – 25 of 49) sorted by relevance

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/third_party/protobuf/objectivec/Tests/
DGPBExtensionRegistryTest.m62 GPBExtensionRegistry *reg1 = [[[GPBExtensionRegistry alloc] init] autorelease];
63 [reg1 addExtension:[UnittestRoot optionalInt32Extension]];
65 GPBExtensionRegistry *reg2 = [[reg1 copy] autorelease];
68 XCTAssertTrue([reg1 extensionForDescriptor:[TestAllExtensions descriptor] fieldNumber:1] ==
75 [reg1 addExtension:[UnittestRoot optionalBoolExtension]];
78 XCTAssertTrue([reg1 extensionForDescriptor:[TestAllExtensions descriptor] fieldNumber:13] ==
80 XCTAssertNil([reg1 extensionForDescriptor:[TestAllExtensions descriptor] fieldNumber:14]);
87 [reg1 addExtension:[UnittestRoot packedInt64Extension]];
90 XCTAssertTrue([reg1 extensionForDescriptor:[TestPackedExtensions descriptor] fieldNumber:91] ==
92 XCTAssertNil([reg1 extensionForDescriptor:[TestPackedExtensions descriptor] fieldNumber:94]);
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/third_party/openssl/crypto/aria/
Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in aria_encrypt() local
490 reg1 = GET_U32_BE(in, 1); in aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
516 reg1 = rk->u[1] ^ MAKE_U32( in aria_encrypt()
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/third_party/openssl/crypto/perlasm/
Dx86gas.pl77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
86 $reg1 = "%$reg1" if ($reg1);
93 $ret .= "($reg1,$reg2,$idx)";
95 elsif ($reg1)
96 { $ret .= "($reg1)"; }
Dx86masm.pl46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
68 $ret .= "+$reg1" if ($reg1 ne "");
71 { $ret .= "$reg1"; }
Dx86nasm.pl43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
69 $ret .= "+$reg1" if ($reg1 ne "");
72 { $ret .= "$reg1"; }
/third_party/pixman/pixman/
Dpixman-arm-neon-asm.h76 .macro pixldst1 op, elem_size, reg1, mem_operand, abits
78 op&.&elem_size {d&reg1}, [&mem_operand&, :&abits&]!
80 op&.&elem_size {d&reg1}, [&mem_operand&]!
84 .macro pixldst2 op, elem_size, reg1, reg2, mem_operand, abits
86 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&, :&abits&]!
88 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&]!
92 .macro pixldst4 op, elem_size, reg1, reg2, reg3, reg4, mem_operand, abits
94 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&, :&abits&]!
96 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&]!
100 .macro pixldst0 op, elem_size, reg1, idx, mem_operand, abits
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Dpixman-region.c295 PREFIX (_equal) (region_type_t *reg1, region_type_t *reg2) in PREFIX()
301 if (reg1->extents.x1 != reg2->extents.x1) in PREFIX()
304 if (reg1->extents.x2 != reg2->extents.x2) in PREFIX()
307 if (reg1->extents.y1 != reg2->extents.y1) in PREFIX()
310 if (reg1->extents.y2 != reg2->extents.y2) in PREFIX()
313 if (PIXREGION_NUMRECTS (reg1) != PIXREGION_NUMRECTS (reg2)) in PREFIX()
316 rects1 = PIXREGION_RECTS (reg1); in PREFIX()
319 for (i = 0; i != PIXREGION_NUMRECTS (reg1); i++) in PREFIX()
749 region_type_t * reg1, /* First region in operation */ in pixman_op() argument
784 if (PIXREGION_NAR (reg1) || PIXREGION_NAR (reg2)) in pixman_op()
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Dpixman-arm-simd-asm.S224 .macro src_0565_8888_2pixels, reg1, reg2
225 and SCRATCH, WK&reg1, MASK @ 00000GGGGGG0000000000gggggg00000
226 bic WK&reg2, WK&reg1, MASK @ RRRRR000000BBBBBrrrrr000000bbbbb
228 mov WK&reg1, WK&reg2, lsl #16 @ rrrrr000000bbbbb0000000000000000
230 bic WK&reg2, WK&reg2, WK&reg1, lsr #16 @ RRRRR000000BBBBB0000000000000000
231 orr WK&reg1, WK&reg1, WK&reg1, lsr #5 @ rrrrrrrrrr0bbbbbbbbbb00000000000
233 pkhtb WK&reg1, WK&reg1, WK&reg1, asr #5 @ rrrrrrrr--------bbbbbbbb--------
234 sel WK&reg1, WK&reg1, SCRATCH @ rrrrrrrrggggggggbbbbbbbb--------
238 orr WK&reg1, STRIDE_M, WK&reg1, lsr #8 @ 11111111rrrrrrrrggggggggbbbbbbbb
452 .macro over_8888_8888_check_transparent numbytes, reg0, reg1, reg2, reg3
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Dpixman-arm-simd-asm.h114 .macro pixldst op, cond=al, numbytes, reg0, reg1, reg2, reg3, base, unaligned=0
118 op&r&cond WK&reg1, [base], #4
122 op&m&cond&ia base!, {WK&reg0,WK&reg1,WK&reg2,WK&reg3}
127 op&r&cond WK&reg1, [base], #4
129 op&m&cond&ia base!, {WK&reg0,WK&reg1}
142 .macro pixst_baseupdated cond, numbytes, reg0, reg1, reg2, reg3, base
144 stm&cond&db base, {WK&reg0,WK&reg1,WK&reg2,WK&reg3}
146 stm&cond&db base, {WK&reg0,WK&reg1}
Dpixman-arm-neon-asm-bilinear.S81 .macro bilinear_load_8888 reg1, reg2, tmp
85 vld1.32 {reg1}, [TMP1], STRIDE
89 .macro bilinear_load_0565 reg1, reg2, tmp
95 convert_four_0565_to_x888_packed reg2, reg1, reg2, tmp
99 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
101 bilinear_load_8888 reg1, reg2, tmp1
102 vmull.u8 acc1, reg1, d28
120 acc1, acc2, reg1, reg2, reg3, reg4, acc2lo, acc2hi
132 convert_0565_to_x888 acc2, reg3, reg2, reg1
133 vzip.u8 reg1, reg3
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Dpixman.h540 pixman_region16_t *reg1,
545 pixman_region16_t *reg1,
571 pixman_region16_t *reg1,
681 pixman_region32_t *reg1,
686 pixman_region32_t *reg1,
712 pixman_region32_t *reg1,
/third_party/ffmpeg/libavutil/mips/
Dmmiutils.h101 #define MMI_LQ(reg1, reg2, addr, bias) \ argument
102 "ld "#reg1", "#bias"("#addr") \n\t" \
105 #define MMI_SQ(reg1, reg2, addr, bias) \ argument
106 "sd "#reg1", "#bias"("#addr") \n\t" \
192 #define MMI_LQ(reg1, reg2, addr, bias) \ argument
193 "gslq "#reg1", "#reg2", "#bias"("#addr") \n\t"
195 #define MMI_SQ(reg1, reg2, addr, bias) \ argument
196 "gssq "#reg1", "#reg2", "#bias"("#addr") \n\t"
/third_party/ffmpeg/libavcodec/mips/
Dvp9_idct_msa.c67 #define VP9_DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \ argument
75 ILVRL_H2_SW((-reg1), reg0, s1_m, s0_m); \
76 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
968 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
999 VP9_DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15); in vp9_idct16_1d_columns_addblk_msa()
1002 reg9 = reg1 - loc2; in vp9_idct16_1d_columns_addblk_msa()
1003 reg1 = reg1 + loc2; in vp9_idct16_1d_columns_addblk_msa()
1016 loc1 = reg1 + reg13; in vp9_idct16_1d_columns_addblk_msa()
1017 reg13 = reg1 - reg13; in vp9_idct16_1d_columns_addblk_msa()
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Dh264pred_msa.c217 v4i32 reg0, reg1, reg2, reg3; in intra_predict_plane_16x16_msa() local
264 reg1 = reg0 + vec6; in intra_predict_plane_16x16_msa()
266 reg2 = reg1 + vec6; in intra_predict_plane_16x16_msa()
271 SRA_4V(reg0, reg1, reg2, reg3, 5); in intra_predict_plane_16x16_msa()
273 PCKEV_H2_SH(reg1, reg0, reg3, reg2, vec11, vec12); in intra_predict_plane_16x16_msa()
/third_party/mesa3d/src/intel/compiler/
Dbrw_fs_bank_conflicts.cpp416 for (unsigned reg1 = reg + 1; reg1 <= max_reg; reg1++) { in require_contiguous() local
417 if (offsets[atoms[reg1]] < reg + n) { in require_contiguous()
418 atoms[reg1] = r; in require_contiguous()
420 if (offsets[atoms[reg1 - 1]] != offsets[atoms[reg1]]) in require_contiguous()
423 offsets[r] = offsets[atoms[reg1]]; in require_contiguous()
424 atoms[reg1] = r; in require_contiguous()
/third_party/ffmpeg/libavcodec/aarch64/
Dvp9mc_16bpp_neon.S326 .macro do_store4 reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, minreg, type
327 sqrshrun \reg1\().4h, \reg1\().4s, #7
337 umin \reg1\().4h, \reg1\().4h, \minreg\().4h
342 urhadd \reg1\().4h, \reg1\().4h, \tmp1\().4h
347 st1 {\reg1\().4h}, [x0], x1
355 .macro do_store8 reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, minreg, type
356 sqrshrun \reg1\().4h, \reg1\().4s, #7
357 sqrshrun2 \reg1\().8h, \reg2\().4s, #7
370 umin \reg1\().8h, \reg1\().8h, \minreg\().8h
375 urhadd \reg1\().8h, \reg1\().8h, \reg5\().8h
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Dvp9mc_neon.S389 .macro do_store4 reg1, reg2, tmp1, tmp2, type
390 sqrshrun \reg1\().8b, \reg1\().8h, #7
397 urhadd \reg1\().8b, \reg1\().8b, \tmp1\().8b
400 st1 {\reg1\().s}[0], [x0], x1
402 st1 {\reg1\().s}[1], [x0], x1
407 .macro do_store reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, type
408 sqrshrun \reg1\().8b, \reg1\().8h, #7
417 urhadd \reg1\().8b, \reg1\().8b, \tmp1\().8b
422 st1 {\reg1\().8b}, [x0], x1
/third_party/ffmpeg/tests/checkasm/aarch64/
Dcheckasm.S151 .macro check_reg_neon reg1, reg2
153 uzp1 v2.2d, v\reg1\().2d, v\reg2\().2d
164 .macro check_reg reg1, reg2
166 eor x0, x0, \reg1
/third_party/mesa3d/src/panfrost/bifrost/
Ddisassemble.c59 return regs.reg0 | ((regs.reg1 & 0x1) << 5); in get_reg0()
61 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0; in get_reg0()
66 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1; in get_reg1()
141 ctrl = regs.reg1 >> 2; in DecodeRegCtrl()
142 decoded.read_reg0 = !(regs.reg1 & 0x2); in DecodeRegCtrl()
Dbi_pack.c221 s.reg1 = regs.slot[1]; in bi_pack_registers()
226 s.reg1 = ctrl << 2; in bi_pack_registers()
230 s.reg1 |= (regs.slot[0] >> 5); in bi_pack_registers()
236 s.reg1 |= (1 << 1); in bi_pack_registers()
/third_party/mesa3d/src/util/
Dregister_allocate.c134 struct ra_reg *reg1 = &regs->regs[r1]; in ra_add_conflict_list() local
136 if (reg1->conflict_list.mem_ctx) { in ra_add_conflict_list()
137 util_dynarray_append(&reg1->conflict_list, unsigned int, r2); in ra_add_conflict_list()
139 BITSET_SET(reg1->conflicts, r2); in ra_add_conflict_list()
180 unsigned int base_reg, unsigned int reg0, unsigned int reg1) in ra_add_transitive_reg_pair_conflict() argument
183 ra_add_reg_conflict(regs, reg1, base_reg); in ra_add_transitive_reg_pair_conflict()
187 if (conflict != reg1) in ra_add_transitive_reg_pair_conflict()
190 ra_add_reg_conflict(regs, reg1, conflict); in ra_add_transitive_reg_pair_conflict()
Dregister_allocate.h66 unsigned int base_reg, unsigned int reg0, unsigned int reg1);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp149 bool haveSameParity(unsigned reg1, unsigned reg2) { in haveSameParity() argument
150 assert(isFPReg(reg1) && "Expecting an FP register for reg1"); in haveSameParity()
153 return isOdd(reg1) == isOdd(reg2); in haveSameParity()
/third_party/ffmpeg/tests/checkasm/arm/
Dcheckasm.S147 .macro check_reg reg1, reg2=
149 eors r2, r2, \reg1
/third_party/ffmpeg/libavcodec/x86/
Dhevc_mc.asm481 %define %%reg1 %7
486 %define %%reg1 m1
506 pmaddubsw %%reg1, %3
508 paddw %%reg1, %%reg3
515 pmaddwd %%reg1, %3
517 paddd %%reg1, %%reg3
519 psrad %%reg1, %1-8
525 packssdw %%reg0, %%reg1

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