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/third_party/protobuf/objectivec/Tests/
DGPBExtensionRegistryTest.m65 GPBExtensionRegistry *reg2 = [[reg1 copy] autorelease];
66 XCTAssertNotNil(reg2);
70 XCTAssertTrue([reg2 extensionForDescriptor:[TestAllExtensions descriptor] fieldNumber:1] ==
76 [reg2 addExtension:[UnittestRoot optionalStringExtension]];
81 XCTAssertNil([reg2 extensionForDescriptor:[TestAllExtensions descriptor] fieldNumber:13]);
82 XCTAssertTrue([reg2 extensionForDescriptor:[TestAllExtensions descriptor] fieldNumber:14] ==
88 [reg2 addExtension:[UnittestRoot packedSint32Extension]];
93 XCTAssertNil([reg2 extensionForDescriptor:[TestPackedExtensions descriptor] fieldNumber:91]);
94 XCTAssertTrue([reg2 extensionForDescriptor:[TestPackedExtensions descriptor] fieldNumber:94] ==
103 GPBExtensionRegistry *reg2 = [[[GPBExtensionRegistry alloc] init] autorelease];
[all …]
/third_party/openssl/crypto/aria/
Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in aria_encrypt() local
491 reg2 = GET_U32_BE(in, 2); in aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
521 reg2 = rk->u[2] ^ MAKE_U32( in aria_encrypt()
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/third_party/openssl/crypto/perlasm/
Dx86gas.pl77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
87 $reg2 = "%$reg2" if ($reg2);
91 if ($reg2)
93 $ret .= "($reg1,$reg2,$idx)";
Dx86masm.pl46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
65 if ($reg2 ne "")
67 $ret .= "$reg2*$idx";
Dx86nasm.pl43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
66 if ($reg2 ne "")
68 $ret .= "$reg2*$idx";
/third_party/pixman/pixman/
Dpixman-region.c295 PREFIX (_equal) (region_type_t *reg1, region_type_t *reg2) in PREFIX()
301 if (reg1->extents.x1 != reg2->extents.x1) in PREFIX()
304 if (reg1->extents.x2 != reg2->extents.x2) in PREFIX()
307 if (reg1->extents.y1 != reg2->extents.y1) in PREFIX()
310 if (reg1->extents.y2 != reg2->extents.y2) in PREFIX()
313 if (PIXREGION_NUMRECTS (reg1) != PIXREGION_NUMRECTS (reg2)) in PREFIX()
317 rects2 = PIXREGION_RECTS (reg2); in PREFIX()
750 region_type_t * reg2, /* 2d region in operation */ in pixman_op() argument
784 if (PIXREGION_NAR (reg1) || PIXREGION_NAR (reg2)) in pixman_op()
799 numRects = PIXREGION_NUMRECTS (reg2); in pixman_op()
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Dpixman-arm-simd-asm.S224 .macro src_0565_8888_2pixels, reg1, reg2 argument
226 bic WK&reg2, WK&reg1, MASK @ RRRRR000000BBBBBrrrrr000000bbbbb
228 mov WK&reg1, WK&reg2, lsl #16 @ rrrrr000000bbbbb0000000000000000
230 bic WK&reg2, WK&reg2, WK&reg1, lsr #16 @ RRRRR000000BBBBB0000000000000000
232 orr WK&reg2, WK&reg2, WK&reg2, lsr #5 @ RRRRRRRRRR0BBBBBBBBBB00000000000
236 pkhtb WK&reg2, WK&reg2, WK&reg2, asr #5 @ RRRRRRRR--------BBBBBBBB--------
237 sel WK&reg2, WK&reg2, SCRATCH @ RRRRRRRRGGGGGGGGBBBBBBBB--------
239 orr WK&reg2, STRIDE_M, WK&reg2, lsr #8 @ 11111111RRRRRRRRGGGGGGGGBBBBBBBB
452 .macro over_8888_8888_check_transparent numbytes, reg0, reg1, reg2, reg3
458 teqeq WK&reg2, #0
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Dpixman-arm-neon-asm.h84 .macro pixldst2 op, elem_size, reg1, reg2, mem_operand, abits
86 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&, :&abits&]!
88 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&]!
92 .macro pixldst4 op, elem_size, reg1, reg2, reg3, reg4, mem_operand, abits
94 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&, :&abits&]!
96 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&]!
104 .macro pixldst3 op, elem_size, reg1, reg2, reg3, mem_operand
105 op&.&elem_size {d&reg1, d&reg2, d&reg3}, [&mem_operand&]!
108 .macro pixldst30 op, elem_size, reg1, reg2, reg3, idx, mem_operand
109 op&.&elem_size {d&reg1[idx], d&reg2[idx], d&reg3[idx]}, [&mem_operand&]!
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Dpixman-arm-neon-asm-bilinear.S81 .macro bilinear_load_8888 reg1, reg2, tmp
86 vld1.32 {reg2}, [TMP1]
89 .macro bilinear_load_0565 reg1, reg2, tmp
93 vld1.32 {reg2[0]}, [TMP1], STRIDE
94 vld1.32 {reg2[1]}, [TMP1]
95 convert_four_0565_to_x888_packed reg2, reg1, reg2, tmp
99 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
101 bilinear_load_8888 reg1, reg2, tmp1
103 vmlal.u8 acc1, reg2, d29
120 acc1, acc2, reg1, reg2, reg3, reg4, acc2lo, acc2hi
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/third_party/ffmpeg/libavutil/mips/
Dmmiutils.h101 #define MMI_LQ(reg1, reg2, addr, bias) \ argument
103 "ld "#reg2", 8+"#bias"("#addr") \n\t"
105 #define MMI_SQ(reg1, reg2, addr, bias) \ argument
107 "sd "#reg2", 8+"#bias"("#addr") \n\t"
192 #define MMI_LQ(reg1, reg2, addr, bias) \ argument
193 "gslq "#reg1", "#reg2", "#bias"("#addr") \n\t"
195 #define MMI_SQ(reg1, reg2, addr, bias) \ argument
196 "gssq "#reg1", "#reg2", "#bias"("#addr") \n\t"
/third_party/ffmpeg/libavcodec/mips/
Dvp9_idct_msa.c967 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
981 VP9_DOTP_CONST_PAIR(reg2, reg14, cospi_28_64, cospi_4_64, reg2, reg14); in vp9_idct16_1d_columns_addblk_msa()
983 BUTTERFLY_4(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2); in vp9_idct16_1d_columns_addblk_msa()
984 VP9_DOTP_CONST_PAIR(reg14, reg2, cospi_16_64, cospi_16_64, loc2, loc3); in vp9_idct16_1d_columns_addblk_msa()
987 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_msa()
989 reg0 = reg2 - loc1; in vp9_idct16_1d_columns_addblk_msa()
990 reg2 = reg2 + loc1; in vp9_idct16_1d_columns_addblk_msa()
1013 loc2 = reg2 + loc1; in vp9_idct16_1d_columns_addblk_msa()
1014 reg15 = reg2 - loc1; in vp9_idct16_1d_columns_addblk_msa()
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/third_party/ffmpeg/libavcodec/aarch64/
Dvp9mc_16bpp_neon.S326 .macro do_store4 reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, minreg, type
328 sqrshrun \reg2\().4h, \reg2\().4s, #7
338 umin \reg2\().4h, \reg2\().4h, \minreg\().4h
343 urhadd \reg2\().4h, \reg2\().4h, \tmp2\().4h
348 st1 {\reg2\().4h}, [x0], x1
355 .macro do_store8 reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, minreg, type
357 sqrshrun2 \reg1\().8h, \reg2\().4s, #7
358 sqrshrun \reg2\().4h, \reg3\().4s, #7
359 sqrshrun2 \reg2\().8h, \reg4\().4s, #7
371 umin \reg2\().8h, \reg2\().8h, \minreg\().8h
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Dvp9mc_neon.S389 .macro do_store4 reg1, reg2, tmp1, tmp2, type
391 sqrshrun \reg2\().8b, \reg2\().8h, #7
398 urhadd \reg2\().8b, \reg2\().8b, \tmp2\().8b
401 st1 {\reg2\().s}[0], [x0], x1
403 st1 {\reg2\().s}[1], [x0], x1
407 .macro do_store reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, type
409 sqrshrun \reg2\().8b, \reg2\().8h, #7
418 urhadd \reg2\().8b, \reg2\().8b, \tmp2\().8b
423 st1 {\reg2\().8b}, [x0], x1
/third_party/ffmpeg/tests/checkasm/aarch64/
Dcheckasm.S151 .macro check_reg_neon reg1, reg2 argument
153 uzp1 v2.2d, v\reg1\().2d, v\reg2\().2d
164 .macro check_reg reg1, reg2 argument
167 eor x1, x1, \reg2
/third_party/mesa3d/src/mesa/drivers/dri/r200/
Dr200_fragshader.c49 GLuint reg2 = 0; in r200SetFragShaderArg() local
54 reg2 |= R200_TXC_REPL_RED << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); in r200SetFragShaderArg()
59 reg2 |= R200_TXC_REPL_GREEN << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); in r200SetFragShaderArg()
65 reg2 |= R200_TXC_REPL_BLUE << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); in r200SetFragShaderArg()
80 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR_SEL_SHIFT; in r200SetFragShaderArg()
85 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR1_SEL_SHIFT; in r200SetFragShaderArg()
109 SET_INST_2(opnum, optype) |= reg2; in r200SetFragShaderArg()
/third_party/mesa3d/src/panfrost/bifrost/
Ddisassemble.c152 else if (regs.reg2 == regs.reg3) in DecodeRegCtrl()
174 fprintf(fp, "slot 2: r%u (write FMA) ", srcs.reg2); in dump_regs()
176 fprintf(fp, "slot 2: r%u (write lo FMA) ", srcs.reg2); in dump_regs()
178 fprintf(fp, "slot 2: r%u (write hi FMA) ", srcs.reg2); in dump_regs()
180 fprintf(fp, "slot 2: r%u (read) ", srcs.reg2); in dump_regs()
210 fprintf(fp, "r%u:t0", next_regs->reg2); in bi_disasm_dest_fma()
375 fprintf(fp, "r%u", srcs.reg2); in dump_src()
/third_party/ffmpeg/tests/checkasm/arm/
Dcheckasm.S147 .macro check_reg reg1, reg2= argument
152 .ifnb \reg2
153 eors r3, r3, \reg2
/third_party/node/test/fixtures/module-load-order/
Dfile3.reg21 exports.file3 = 'file3.reg2';
Dfile2.reg21 exports.file2 = 'file2.reg2';
Dfile4.reg21 exports.file4 = 'file4.reg2';
Dfile5.reg21 exports.file5 = 'file5.reg2';
Dfile1.reg21 exports.file1 = 'file1.reg2';
/third_party/node/test/fixtures/module-load-order/file9/
Dindex.reg21 exports.file9 = 'file9/index.reg2';
/third_party/node/test/fixtures/module-load-order/file8/
Dindex.reg21 exports.file8 = 'file8/index.reg2';
/third_party/node/test/fixtures/module-load-order/file2/
Dindex.reg21 exports.file2 = 'file2/index.reg2';

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