| /third_party/skia/third_party/externals/spirv-tools/source/opt/ |
| D | register_pressure.cpp | 217 size_t reg_count = live_inout->live_out_.size(); in EvaluateRegisterRequirements() local
221 live_inout->used_registers_ = reg_count; in EvaluateRegisterRequirements()
232 [live_inout, &die_in_block, ®_count, this](uint32_t* id) { in EvaluateRegisterRequirements()
241 reg_count++; in EvaluateRegisterRequirements()
246 std::max(live_inout->used_registers_, reg_count); in EvaluateRegisterRequirements()
248 reg_count--; in EvaluateRegisterRequirements()
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| /third_party/spirv-tools/source/opt/ |
| D | register_pressure.cpp | 217 size_t reg_count = live_inout->live_out_.size(); in EvaluateRegisterRequirements() local
221 live_inout->used_registers_ = reg_count; in EvaluateRegisterRequirements()
232 [live_inout, &die_in_block, ®_count, this](uint32_t* id) { in EvaluateRegisterRequirements()
241 reg_count++; in EvaluateRegisterRequirements()
246 std::max(live_inout->used_registers_, reg_count); in EvaluateRegisterRequirements()
248 reg_count--; in EvaluateRegisterRequirements()
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| /third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/source/opt/ |
| D | register_pressure.cpp | 217 size_t reg_count = live_inout->live_out_.size(); in EvaluateRegisterRequirements() local
221 live_inout->used_registers_ = reg_count; in EvaluateRegisterRequirements()
232 [live_inout, &die_in_block, ®_count, this](uint32_t* id) { in EvaluateRegisterRequirements()
241 reg_count++; in EvaluateRegisterRequirements()
246 std::max(live_inout->used_registers_, reg_count); in EvaluateRegisterRequirements()
248 reg_count--; in EvaluateRegisterRequirements()
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| /third_party/mesa3d/src/util/ |
| D | register_allocate.c | 430 unsigned int reg_count = blob_read_uint32(blob); in ra_set_deserialize() local
434 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, reg_count, false); in ra_set_deserialize()
435 assert(regs->count == reg_count); in ra_set_deserialize()
443 for (unsigned int r = 0; r < reg_count; r++) { in ra_set_deserialize()
445 blob_copy_bytes(blob, reg->conflicts, BITSET_WORDS(reg_count) * in ra_set_deserialize()
460 class->regs = ralloc_array(class, BITSET_WORD, BITSET_WORDS(reg_count)); in ra_set_deserialize()
461 blob_copy_bytes(blob, class->regs, BITSET_WORDS(reg_count) * in ra_set_deserialize()
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| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3.c | 211 unsigned reg_count, bool double_threadsize) in ir3_get_reg_dependent_max_waves() argument
213 return reg_count ? (compiler->reg_size_vec4 / in ir3_get_reg_dependent_max_waves()
214 (reg_count * (double_threadsize ? 2 : 1)) * in ir3_get_reg_dependent_max_waves()
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| D | ir3_ra.c | 2044 unsigned reg_count = DIV_ROUND_UP(pressure, 2 * 4); in calc_target_full_pressure() local
2046 bool double_threadsize = ir3_should_double_threadsize(v, reg_count); in calc_target_full_pressure()
2048 unsigned target = reg_count; in calc_target_full_pressure()
2052 v->shader->compiler, reg_count, double_threadsize); in calc_target_full_pressure()
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| D | ir3.h | 642 unsigned reg_count,
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| D | ir2_private.h | 179 unsigned reg_count; member
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| D | ir2_nir.c | 354 reg = share_reg ? share_reg->reg : &ctx->reg[ctx->reg_count++]; in instr_create_alu_reg()
1168 ctx->reg_count = MAX2(ctx->reg_count, reg->index + 1); in ir2_nir_compile()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_fs.cpp | 2125 int reg_count = 0; in split_virtual_grfs() local
2128 vgrf_to_reg[i] = reg_count; in split_virtual_grfs()
2129 reg_count += alloc.sizes[i]; in split_virtual_grfs()
2138 bool *split_points = new bool[reg_count]; in split_virtual_grfs()
2139 memset(split_points, 0, reg_count * sizeof(*split_points)); in split_virtual_grfs()
2184 int *new_virtual_grf = new int[reg_count]; in split_virtual_grfs()
2185 int *new_reg_offset = new int[reg_count]; in split_virtual_grfs()
2220 assert(reg == reg_count); in split_virtual_grfs()
7078 unsigned reg_count = DIV_ROUND_UP(inst->size_written, REG_SIZE); in get_fpu_lowered_simd_width() local
7081 reg_count = MAX2(reg_count, DIV_ROUND_UP(inst->size_read(i), REG_SIZE)); in get_fpu_lowered_simd_width()
[all …]
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_cmd_buffer.c | 2145 unsigned reg_offset = 0, reg_count = 0; in radv_load_ds_clear_metadata() local
2150 ++reg_count; in radv_load_ds_clear_metadata()
2156 ++reg_count; in radv_load_ds_clear_metadata()
2165 radeon_emit(cs, reg_count); in radv_load_ds_clear_metadata()
2169 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0)); in radv_load_ds_clear_metadata()
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