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Searched refs:reg_map (Results 1 – 17 of 17) sorted by relevance

/third_party/pcre2/pcre2/src/sljit/
DsljitNativeX86_32.c115 PUSH_REG(reg_map[TMP_REG1]); in sljit_emit_enter()
119 *inst++ = MOD_REG | (reg_map[TMP_REG1] << 3) | 0x4 /* esp */; in sljit_emit_enter()
123 PUSH_REG(reg_map[SLJIT_S2]); in sljit_emit_enter()
125 PUSH_REG(reg_map[SLJIT_S1]); in sljit_emit_enter()
127 PUSH_REG(reg_map[SLJIT_S0]); in sljit_emit_enter()
132 inst[1] = MOD_REG | (reg_map[SLJIT_S0] << 3) | reg_map[SLJIT_R2]; in sljit_emit_enter()
137 inst[1] = MOD_REG | (reg_map[SLJIT_S1] << 3) | reg_map[SLJIT_R1]; in sljit_emit_enter()
142 inst[1] = MOD_DISP8 | (reg_map[SLJIT_S2] << 3) | 0x4 /* esp */; in sljit_emit_enter()
149 inst[1] = MOD_DISP8 | (reg_map[SLJIT_S0] << 3) | reg_map[TMP_REG1]; in sljit_emit_enter()
155 inst[1] = MOD_DISP8 | (reg_map[SLJIT_S1] << 3) | reg_map[TMP_REG1]; in sljit_emit_enter()
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DsljitNativeX86_64.c36 *inst++ = REX_W | ((reg_map[reg] <= 7) ? 0 : REX_B); in emit_load_imm64()
37 *inst++ = MOV_r_i32 + (reg_map[reg] & 0x7); in emit_load_imm64()
49 SLJIT_ASSERT(reg_map[TMP_REG2] >= 8); in generate_far_jump_code()
156 size = reg_map[i] >= 8 ? 2 : 1; in sljit_emit_enter()
160 if (reg_map[i] >= 8) in sljit_emit_enter()
166 size = reg_map[i] >= 8 ? 2 : 1; in sljit_emit_enter()
170 if (reg_map[i] >= 8) in sljit_emit_enter()
188 inst[2] = MOD_REG | (reg_map[SLJIT_S0] << 3) | 0x7 /* rdi */; in sljit_emit_enter()
206 inst[2] = MOD_REG | (reg_map[SLJIT_S0] << 3) | 0x1 /* rcx */; in sljit_emit_enter()
212 inst[2] = MOD_REG | (reg_map[SLJIT_S1] << 3) | 0x2 /* rdx */; in sljit_emit_enter()
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DsljitNativeX86_common.c73 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 3] = { variable
98 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 4] = { variable
107 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 4] = { variable
754 *inst++ = REX_W | (reg_map[reg] <= 7 ? 0 : REX_B); in emit_rdssp()
758 *inst = (0x3 << 6) | (0x1 << 3) | (reg_map[reg] & 0x7); in emit_rdssp()
778 *inst++ = REX_W | (reg_map[reg] <= 7 ? 0 : REX_B); in emit_incssp()
782 *inst = (0x3 << 6) | (0x5 << 3) | (reg_map[reg] & 0x7); in emit_incssp()
811 SLJIT_ASSERT(reg_map[TMP_REG1] == 5); in adjust_shadow_stack()
893 return emit_do_imm(compiler, MOV_r_i32 + reg_map[dst], srcw); in emit_mov()
900 … return emit_do_imm32(compiler, (reg_map[dst] >= 8) ? REX_B : 0, MOV_r_i32 + reg_lmap[dst], srcw); in emit_mov()
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DsljitNativeARM_T2_32.c48 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 5] = { variable
60 #define RD3(rd) (reg_map[rd])
61 #define RN3(rn) (reg_map[rn] << 3)
62 #define RM3(rm) (reg_map[rm] << 6)
63 #define RDN3(rdn) (reg_map[rdn] << 8)
69 ((reg_map[rn] << 3) | (reg_map[rd] & 0x7) | ((reg_map[rd] & 0x8) << 4))
71 (reg_map[reg1] <= 7 && reg_map[reg2] <= 7)
73 (reg_map[reg1] <= 7 && reg_map[reg2] <= 7 && reg_map[reg3] <= 7)
76 #define RD4(rd) (reg_map[rd] << 8)
77 #define RN4(rn) (reg_map[rn] << 16)
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DsljitNativeARM_32.c63 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 5] = { variable
71 #define RM(rm) (reg_map[rm])
72 #define RD(rd) (reg_map[rd] << 12)
73 #define RN(rn) (reg_map[rn] << 16)
273 SLJIT_ASSERT(reg_map[TMP_REG1] != 14); in emit_blx()
1033 push |= 1 << reg_map[i]; in sljit_emit_enter()
1036 push |= 1 << reg_map[i]; in sljit_emit_enter()
1093 pop |= 1 << reg_map[i]; in sljit_emit_return()
1096 pop |= 1 << reg_map[i]; in sljit_emit_return()
1134 …(reg_map[(flags & ARGS_SWAPPED) ? src1 : src2] << 8) | (opcode << 5) | 0x10 | RM((flags & ARGS_SWA…
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DsljitNativeARM_64.c46 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 8] = { variable
55 #define RD(rd) (reg_map[rd])
56 #define RT(rt) (reg_map[rt])
57 #define RN(rn) (reg_map[rn] << 5)
58 #define RT2(rt2) (reg_map[rt2] << 10)
59 #define RM(rm) (reg_map[rm] << 16)
1334 SLJIT_ASSERT(reg_map[1] == 0 && reg_map[3] == 2 && reg_map[5] == 4); in sljit_emit_op_src()
1356 return reg_map[reg]; in sljit_get_register_index()
DsljitNativeSPARC_common.c100 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 6] = { variable
112 #define D(d) (reg_map[d] << 25)
116 #define S1(s1) (reg_map[s1] << 14)
119 #define S2(s2) (reg_map[s2])
127 #define DR(dr) (reg_map[dr])
1008 return reg_map[reg]; in sljit_get_register_index()
DsljitNativePPC_common.c107 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 7] = { variable
118 #define D(d) (reg_map[d] << 21)
119 #define S(s) (reg_map[s] << 21)
120 #define A(a) (reg_map[a] << 16)
121 #define B(b) (reg_map[b] << 11)
122 #define C(c) (reg_map[c] << 6)
1614 return reg_map[reg]; in sljit_get_register_index()
DsljitNativeMIPS_common.c82 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 5] = { variable
104 #define S(s) (reg_map[s] << 21)
105 #define T(t) (reg_map[t] << 16)
106 #define D(d) (reg_map[d] << 11)
117 #define DR(dr) (reg_map[dr])
1505 return reg_map[reg]; in sljit_get_register_index()
DsljitNativeSPARC_32.c156 reg = reg_map[*src & REG_MASK]; in call_with_args()
DsljitNativeS390X.c47 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 4] = { variable
123 SLJIT_ASSERT(r >= 0 && r < (sljit_s32)(sizeof(reg_map) / sizeof(reg_map[0]))); in gpr()
124 return reg_map[r]; in gpr()
DsljitNativeMIPS_32.c456 SLJIT_ASSERT(reg_map[TMP_REG1] == 4 && freg_map[TMP_FREG1] == 12); in call_with_args()
DsljitNativeMIPS_64.c554 SLJIT_ASSERT(reg_map[TMP_REG1] == 4 && freg_map[TMP_FREG1] == 12); in call_with_args()
/third_party/mesa3d/src/etnaviv/drm-shim/
Detnaviv_noop.c39 const uint64_t *reg_map; member
45 .reg_map = (const uint64_t[]){
72 .reg_map = (const uint64_t[]){
99 .reg_map = (const uint64_t[]){
126 .reg_map = (const uint64_t[]){
198 gp->value = shim_gpu->reg_map[gp->param]; in etnaviv_ioctl_get_param()
/third_party/mesa3d/src/compiler/nir/
Dnir_schedule.c132 struct hash_table *reg_map; member
246 struct hash_entry *entry = _mesa_hash_table_search(state->reg_map, in nir_schedule_reg_src_deps()
273 struct hash_entry *entry = _mesa_hash_table_search(state->reg_map, in nir_schedule_reg_dest_deps()
276 _mesa_hash_table_insert(state->reg_map, dest->reg.reg, dest_n); in nir_schedule_reg_dest_deps()
315 ralloc(state->reg_map, struct nir_schedule_class_dep); in nir_schedule_get_class_dep()
496 .reg_map = _mesa_pointer_hash_table_create(NULL), in calculate_forward_deps()
505 ralloc_free(state.reg_map); in calculate_forward_deps()
514 .reg_map = _mesa_pointer_hash_table_create(NULL), in calculate_reverse_deps()
523 ralloc_free(state.reg_map); in calculate_reverse_deps()
/third_party/mesa3d/src/broadcom/drm-shim/
Dv3dx.c264 static const uint32_t reg_map[] = { in v3dX() local
280 if (gp->param < ARRAY_SIZE(reg_map) && reg_map[gp->param]) { in v3dX()
281 gp->value = V3D_READ(reg_map[gp->param]); in v3dX()
/third_party/mesa3d/src/broadcom/simulator/
Dv3dx_simulator.c249 static const uint32_t reg_map[] = { in v3dX() local
274 if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) { in v3dX()
275 args->value = V3D_READ(reg_map[args->param]); in v3dX()