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Searched refs:reg_size (Results 1 – 16 of 16) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/iris/
Diris_perf.c60 uint32_t reg, uint32_t reg_size, in iris_perf_store_register_mem() argument
65 if (reg_size == 8) { in iris_perf_store_register_mem()
68 assert(reg_size == 4); in iris_perf_store_register_mem()
79 uint32_t reg, uint32_t reg_size,
/third_party/mesa3d/src/freedreno/ir3/
Dir3_ra_validate.c142 unsigned dst_max = ra_reg_get_physreg(dst) + reg_size(dst); in validate_simple()
149 unsigned src_max = ra_reg_get_physreg(src) + reg_size(src); in validate_simple()
224 for (unsigned i = 0; i < reg_size(dst); i++) { in propagate_normal_instr()
255 unsigned size = reg_size(dst); in propagate_collect()
283 size += reg_size(pcopy->srcs[i]); in propagate_parallelcopy()
294 for (unsigned j = 0; j < reg_size(dst); j++) { in propagate_parallelcopy()
306 offset += reg_size(dst); in propagate_parallelcopy()
316 for (unsigned j = 0; j < reg_size(dst); j++) in propagate_parallelcopy()
319 offset += reg_size(dst); in propagate_parallelcopy()
444 for (unsigned i = 0; i < reg_size(src); i++) { in check_reaching_src()
Dir3_merge_regs.c125 value.offset + value.size > reg_size(value.reg)) in chase_copies()
155 unsigned a_end = a_start + reg_size(a->reg); in can_skip_interference()
156 unsigned b_end = b_start + reg_size(b->reg); in can_skip_interference()
202 set->size = reg_size(def); in get_merge_set()
489 unsigned size = reg_size(dst); in index_merge_sets()
Dir3_ra.c737 for (unsigned i = 0; i < reg_size(reg); i++) { in get_reg_specified()
763 for (unsigned i = 0; i < reg_size(reg); i++) { in try_evict_regs()
773 conflicting->physreg_start < physreg + reg_size(reg); in try_evict_regs()
1133 unsigned size = reg_size(reg); in get_reg()
1154 if (ra_get_file(ctx, src) == file && reg_size(src) >= size) { in get_reg()
1194 return compress_regs_left(ctx, file, reg_size(reg), reg_elem_size(reg), in get_reg()
1250 interval->physreg_end = physreg + reg_size(dst); in allocate_dst_fixed()
1442 if (reg_size(interval->interval.reg) >= reg_size(instr->dsts[0])) { in handle_collect()
1663 interval->physreg_end = physreg + reg_size(def); in handle_live_in()
2069 unsigned size = reg_size(reg); in add_pressure()
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Dir3_spill.c167 ctx->limit_pressure.full -= reg_size(ctx->base_reg); in add_base_reg()
390 unsigned size = reg_size(interval->interval.reg); in interval_add()
417 unsigned size = reg_size(interval->interval.reg); in interval_delete()
507 physreg_t max = physreg + reg_size(dst); in insert_dst()
615 ctx->spill_slot = reg->spill_slot + reg_size(reg) * 2; in get_spill_slot()
769 def->interval_end = set->interval_start + offset + reg_size(def); in add_to_merge_set()
1035 reg->interval_end = offset + reg_size(def); in create_temp_interval()
1043 ctx->live->interval_offset += reg_size(def); in create_temp_interval()
Dir3.h1073 reg_size(const struct ir3_register *reg) in reg_size() function
/third_party/mesa3d/src/intel/compiler/
Dbrw_fs_reg_allocate.cpp745 const unsigned reg_size = dst.component_size(bld.dispatch_width()) / in emit_unspill() local
747 assert(count % reg_size == 0); in emit_unspill()
749 for (unsigned i = 0; i < count / reg_size; i++) { in emit_unspill()
774 unspill_inst->size_written = reg_size * REG_SIZE; in emit_unspill()
781 BRW_DATAPORT_OWORD_BLOCK_DWORDS(reg_size * 8)); in emit_unspill()
800 dst.offset += reg_size * REG_SIZE; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
810 const unsigned reg_size = src.component_size(bld.dispatch_width()) / in emit_spill() local
812 assert(count % reg_size == 0); in emit_spill()
814 for (unsigned i = 0; i < count / reg_size; i++) { in emit_spill()
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Dbrw_ir_vec4.h434 const unsigned reg_size = in regs_read() local
436 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + inst->size_read(i), in regs_read()
437 reg_size); in regs_read()
Dbrw_ir_fs.h466 const unsigned reg_size = inst->src[i].file == UNIFORM ? 4 : REG_SIZE; in regs_read() local
467 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + in regs_read()
470 reg_size); in regs_read()
Dbrw_vec4.cpp1663 const unsigned reg_size = (inst->dst.file == UNIFORM ? 16 : REG_SIZE); in dump_instruction() local
1664 fprintf(file, "+%d.%d", inst->dst.offset / reg_size, in dump_instruction()
1665 inst->dst.offset % reg_size); in dump_instruction()
1756 const unsigned reg_size = (inst->src[i].file == UNIFORM ? 16 : REG_SIZE); in dump_instruction() local
1757 fprintf(file, "+%d.%d", inst->src[i].offset / reg_size, in dump_instruction()
1758 inst->src[i].offset % reg_size); in dump_instruction()
Dbrw_fs_nir.cpp79 unsigned reg_size = vec4s[loc]; in nir_setup_outputs() local
84 for (unsigned i = 1; i < reg_size; i++) { in nir_setup_outputs()
86 reg_size = MAX2(vec4s[i + loc] + i, reg_size); in nir_setup_outputs()
89 fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_F, 4 * reg_size); in nir_setup_outputs()
90 for (unsigned i = 0; i < reg_size; i++) { in nir_setup_outputs()
95 loc += reg_size; in nir_setup_outputs()
Dbrw_fs.cpp8171 const unsigned reg_size = (inst->dst.file == UNIFORM ? 4 : REG_SIZE); in dump_instruction() local
8172 fprintf(file, "+%d.%d", inst->dst.offset / reg_size, in dump_instruction()
8173 inst->dst.offset % reg_size); in dump_instruction()
8270 const unsigned reg_size = (inst->src[i].file == UNIFORM ? 4 : REG_SIZE); in dump_instruction() local
8271 fprintf(file, "+%d.%d", inst->src[i].offset / reg_size, in dump_instruction()
8272 inst->src[i].offset % reg_size); in dump_instruction()
/third_party/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_performance_query.c459 uint32_t reg, uint32_t reg_size, in brw_perf_store_register() argument
462 if (reg_size == 8) { in brw_perf_store_register()
465 assert(reg_size == 4); in brw_perf_store_register()
471 uint32_t reg, uint32_t reg_size,
/third_party/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_compiler_tgsi.c130 size_t reg_size; member
270 for (int idx = 0; idx < file->reg_size; ++idx) { in sort_registers()
316 for (int idx = 0; idx < file->reg_size; ++idx) in assign_temporaries_to_native()
525 c->file[x].reg_size = c->info.file_max[x] + 1; in etna_allocate_decls()
527 for (int sub = 0; sub < c->file[x].reg_size; ++sub) { in etna_allocate_decls()
1929 for (int idx = 0; idx < c->file[file].reg_size; ++idx) { in find_decl_by_semantic()
2011 for (int idx = 0; idx < file->reg_size; ++idx) { in assign_uniforms()
2030 c->imm_base = c->file[TGSI_FILE_CONSTANT].reg_size * 4; in assign_constants_and_immediates()
2045 for (int idx = 0; idx < c->file[TGSI_FILE_SAMPLER].reg_size; ++idx) { in assign_texture_units()
2106 for (int idx = 0; idx < c->file[TGSI_FILE_INPUT].reg_size; ++idx) { in permute_ps_inputs()
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/third_party/mesa3d/src/intel/perf/
Dintel_perf.h380 … void (*store_register_mem)(void *ctx, void *bo, uint32_t reg, uint32_t reg_size, uint32_t offset);
/third_party/mesa3d/docs/relnotes/
D21.2.0.rst1448 - ir3: Add reg_elems(), reg_elem_size(), and reg_size()