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Searched refs:reg_val (Results 1 – 5 of 5) sorted by relevance

/third_party/mesa3d/src/freedreno/decode/
Dcffdec.c329 reg_val(uint32_t regbase) in reg_val() function
360 printf("%s:%u,%u,%u,%u\n", levels[level], reg_val(r + 4), reg_val(r + 5), in reg_dump_scratch()
361 reg_val(r + 6), reg_val(r + 7)); in reg_dump_scratch()
502 return reg_val(regbase(count_reg)); in get_tex_count()
837 gpuaddr = (((uint64_t)reg_val(regbase + 1)) << 32) | dword; in dump_register_val()
841 gpuaddr = (((uint64_t)dword) << 32) | reg_val(regbase - 1); in dump_register_val()
843 gpuaddr = (((uint64_t)reg_val(regbase + 1)) << 32) | dword; in dump_register_val()
878 uint64_t qword = (((uint64_t)reg_val(regbase + 1)) << 32) | dword; in dump_register()
1009 uint32_t lastval = reg_val(regbase); in skip_query()
1025 uint32_t scissor_tl = reg_val(regbase("GRAS_SC_WINDOW_SCISSOR_TL")); in __do_query()
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Dcffdec.h88 uint32_t reg_val(uint32_t regbase);
Dcrashdec.c97 uint64_t val = reg_val(reg); in regval64()
99 val |= ((uint64_t)reg_val(reg + 1)) << 32; in regval64()
108 return reg_val(reg); in regval()
Dscript.c80 return reg_val(regbase); in rnn_val()
557 lua_pushnumber(L, reg_val(regbase)); in l_reg_val()
/third_party/mesa3d/src/gallium/drivers/r600/
Devergreen_state.c4817 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; in evergreen_emit_set_append_cnt() local
4820 radeon_emit(cs, (reg_val << 16) | 0x3); in evergreen_emit_set_append_cnt()
4840 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2; in evergreen_emit_event_write_eos() local
4849 radeon_emit(cs, reg_val); in evergreen_emit_event_write_eos()