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/third_party/libunwind/src/aarch64/
DGresume.c43 unsigned long regs[24]; in aarch64_local_resume() local
44 regs[0] = uc->uc_mcontext.regs[0]; in aarch64_local_resume()
45 regs[1] = uc->uc_mcontext.regs[1]; in aarch64_local_resume()
46 regs[2] = uc->uc_mcontext.regs[2]; in aarch64_local_resume()
47 regs[3] = uc->uc_mcontext.regs[3]; in aarch64_local_resume()
48 regs[4] = uc->uc_mcontext.regs[19]; in aarch64_local_resume()
49 regs[5] = uc->uc_mcontext.regs[20]; in aarch64_local_resume()
50 regs[6] = uc->uc_mcontext.regs[21]; in aarch64_local_resume()
51 regs[7] = uc->uc_mcontext.regs[22]; in aarch64_local_resume()
52 regs[8] = uc->uc_mcontext.regs[23]; in aarch64_local_resume()
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Dgen-offsets.c30 SC ("R0", regs[0]); in main()
31 SC ("R1", regs[1]); in main()
32 SC ("R2", regs[2]); in main()
33 SC ("R3", regs[3]); in main()
34 SC ("R4", regs[4]); in main()
35 SC ("R5", regs[5]); in main()
36 SC ("R6", regs[6]); in main()
37 SC ("R7", regs[7]); in main()
38 SC ("R8", regs[8]); in main()
39 SC ("R9", regs[9]); in main()
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/third_party/libunwind/src/arm/
DGresume.c43 unsigned long regs[10]; in arm_local_resume() local
44 regs[0] = uc->regs[4]; in arm_local_resume()
45 regs[1] = uc->regs[5]; in arm_local_resume()
46 regs[2] = uc->regs[6]; in arm_local_resume()
47 regs[3] = uc->regs[7]; in arm_local_resume()
48 regs[4] = uc->regs[8]; in arm_local_resume()
49 regs[5] = uc->regs[9]; in arm_local_resume()
50 regs[6] = uc->regs[10]; in arm_local_resume()
51 regs[7] = uc->regs[11]; /* FP */ in arm_local_resume()
52 regs[8] = uc->regs[13]; /* SP */ in arm_local_resume()
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/third_party/mesa3d/src/util/
Dregister_allocate.c95 struct ra_regs *regs; in ra_alloc_reg_set() local
97 regs = rzalloc(mem_ctx, struct ra_regs); in ra_alloc_reg_set()
98 regs->count = count; in ra_alloc_reg_set()
99 regs->regs = rzalloc_array(regs, struct ra_reg, count); in ra_alloc_reg_set()
102 regs->regs[i].conflicts = rzalloc_array(regs->regs, BITSET_WORD, in ra_alloc_reg_set()
104 BITSET_SET(regs->regs[i].conflicts, i); in ra_alloc_reg_set()
106 util_dynarray_init(&regs->regs[i].conflict_list, in ra_alloc_reg_set()
107 need_conflict_lists ? regs->regs : NULL); in ra_alloc_reg_set()
109 util_dynarray_append(&regs->regs[i].conflict_list, unsigned int, i); in ra_alloc_reg_set()
112 return regs; in ra_alloc_reg_set()
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Dregister_allocate_test.cpp49 thumb_checks(struct ra_regs *regs, unsigned reg32_base, unsigned reg64_base) in thumb_checks() argument
51 struct ra_class *reg32low = ra_get_class_from_index(regs, 0); in thumb_checks()
52 struct ra_class *reg64low = ra_get_class_from_index(regs, 1); in thumb_checks()
53 struct ra_class *reg96 = ra_get_class_from_index(regs, 2); in thumb_checks()
88 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, 100, true); in TEST_F() local
95 struct ra_class *reg32low = ra_alloc_reg_class(regs); in TEST_F()
99 ra_add_transitive_reg_conflict(regs, i, vreg); in TEST_F()
104 struct ra_class *reg64low = ra_alloc_reg_class(regs); in TEST_F()
108 ra_add_transitive_reg_conflict(regs, i, vreg); in TEST_F()
109 ra_add_transitive_reg_conflict(regs, (i + 1) % 8, vreg); in TEST_F()
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Dregister_allocate.h55 void ra_set_allocate_round_robin(struct ra_regs *regs);
56 struct ra_class *ra_alloc_reg_class(struct ra_regs *regs);
57 struct ra_class *ra_alloc_contig_reg_class(struct ra_regs *regs, int contig_len);
59 void ra_add_reg_conflict(struct ra_regs *regs,
61 void ra_add_transitive_reg_conflict(struct ra_regs *regs,
65 ra_add_transitive_reg_pair_conflict(struct ra_regs *regs,
68 void ra_make_reg_conflicts_transitive(struct ra_regs *regs, unsigned int reg);
70 struct ra_class *ra_get_class_from_index(struct ra_regs *regs, unsigned int c);
71 void ra_set_num_conflicts(struct ra_regs *regs, unsigned int class_a,
73 void ra_set_finalize(struct ra_regs *regs, unsigned int **conflicts);
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/third_party/gstreamer/gstplugins_good/gst/goom/
Dmmx.h324 #define mmx_r2r(op, regs, regd) \ argument
327 __asm__ __volatile__ ("movq %%" #regs ", %0" \
330 printf(#op "_r2r(" #regs "=0x%08x%08x, ", \
337 __asm__ __volatile__ (#op " %" #regs ", %" #regd); \
384 #define mmx_r2r(op, regs, regd) \ argument
385 __asm__ __volatile__ (#op " %" #regs ", %" #regd)
403 #define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd) argument
418 #define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd) argument
429 #define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd) argument
433 #define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd) argument
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Dxmmx.h317 #define mmx_r2r(op, regs, regd) \ argument
320 __asm__ __volatile__ ("movq %%" #regs ", %0" \
323 fprintf(stderr, #op "_r2r(" #regs "=0x%08x%08x, ", \
330 __asm__ __volatile__ (#op " %" #regs ", %" #regd); \
382 #define mmx_r2r(op, regs, regd) \ argument
383 __asm__ __volatile__ (#op " %" #regs ", %" #regd)
407 #define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd) argument
422 #define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd) argument
434 #define pmagw_r2r(regs, regd) mmx_r2r(pmagw, regs, regd) argument
458 #define pmulhrw_r2r(regs, regd) mmx_r2r(pmulhrw, regs, regd) argument
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/third_party/flutter/skia/third_party/externals/sdl/src/render/
Dmmx.h239 #define mmx_r2r(op, regs, regd) \ argument
242 __asm__ __volatile__ ("movq %%" #regs ", %0" \
245 printf(#op "_r2r(" #regs "=0x%08x%08x, ", \
252 __asm__ __volatile__ (#op " %" #regs ", %" #regd); \
299 #define mmx_r2r(op, regs, regd) \ argument
300 __asm__ __volatile__ (#op " %" #regs ", %" #regd)
318 #define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd) argument
333 #define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd) argument
344 #define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd) argument
348 #define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd) argument
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/third_party/gstreamer/gstplugins_good/gst/deinterlace/tvtime/
Dmmx.h327 #define mmx_r2r(op, regs, regd) \ argument
330 __asm__ __volatile__ ("movq %%" #regs ", %0" \
333 fprintf(stderr, #op "_r2r(" #regs "=0x%016llx, ", mmx_trace.q); \
338 __asm__ __volatile__ (#op " %" #regs ", %" #regd); \
381 #define mmx_r2r(op, regs, regd) \ argument
382 __asm__ __volatile__ (#op " %" #regs ", %" #regd)
400 #define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd) argument
415 #define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd) argument
426 #define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd) argument
430 #define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd) argument
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Dsse.h307 #define sse_r2r(op, regs, regd) \ argument
310 __asm__ __volatile__ ("movq %%" #regs ", %0" \
313 fprintf(stderr, #op "_r2r(" #regs "=0x%08x%08x, ", \
320 __asm__ __volatile__ (#op " %" #regs ", %" #regd); \
367 #define sse_r2r(op, regs, regd) \ argument
368 __asm__ __volatile__ (#op " %" #regs ", %" #regd)
370 #define sse_r2ri(op, regs, regd, imm) \ argument
371 __asm__ __volatile__ (#op " %0, %%" #regs ", %%" #regd \
403 #define movaps_r2r(regs, regd) sse_r2r(movaps, regs, regd) argument
425 #define movups_r2r(regs, regd) sse_r2r(movups, regs, regd) argument
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/third_party/mesa3d/src/panfrost/bifrost/
Dbi_pack.c64 bi_assign_slot_read(bi_registers *regs, bi_index src) in bi_assign_slot_read() argument
72 if (regs->slot[i] == src.value && regs->enabled[i]) in bi_assign_slot_read()
76 if (regs->slot[2] == src.value && regs->slot23.slot2 == BIFROST_OP_READ) in bi_assign_slot_read()
82 if (!regs->enabled[i]) { in bi_assign_slot_read()
83 regs->slot[i] = src.value; in bi_assign_slot_read()
84 regs->enabled[i] = true; in bi_assign_slot_read()
89 if (!regs->slot23.slot3) { in bi_assign_slot_read()
90 regs->slot[2] = src.value; in bi_assign_slot_read()
91 regs->slot23.slot2 = BIFROST_OP_READ; in bi_assign_slot_read()
95 bi_print_slots(regs, stderr); in bi_assign_slot_read()
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Dbi_print.c44 bi_print_slots(bi_registers *regs, FILE *fp) in bi_print_slots() argument
47 if (regs->enabled[i]) in bi_print_slots()
48 fprintf(fp, "slot %u: %u\n", i, regs->slot[i]); in bi_print_slots()
51 if (regs->slot23.slot2) { in bi_print_slots()
53 bi_reg_op_name(regs->slot23.slot2), in bi_print_slots()
54 regs->slot23.slot2 >= BIFROST_OP_WRITE ? in bi_print_slots()
56 regs->slot[2]); in bi_print_slots()
59 if (regs->slot23.slot3) { in bi_print_slots()
61 bi_reg_op_name(regs->slot23.slot3), in bi_print_slots()
62 regs->slot23.slot3_fma ? "FMA" : "ADD", in bi_print_slots()
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Ddisassemble.c56 static unsigned get_reg0(struct bifrost_regs regs) in get_reg0() argument
58 if (regs.ctrl == 0) in get_reg0()
59 return regs.reg0 | ((regs.reg1 & 0x1) << 5); in get_reg0()
61 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0; in get_reg0()
64 static unsigned get_reg1(struct bifrost_regs regs) in get_reg1() argument
66 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1; in get_reg1()
136 static struct bifrost_reg_ctrl DecodeRegCtrl(FILE *fp, struct bifrost_regs regs, bool first) in DecodeRegCtrl() argument
140 if (regs.ctrl == 0) { in DecodeRegCtrl()
141 ctrl = regs.reg1 >> 2; in DecodeRegCtrl()
142 decoded.read_reg0 = !(regs.reg1 & 0x2); in DecodeRegCtrl()
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/third_party/mesa3d/src/freedreno/vulkan/
Dtu_cs.h329 #define __ONE_REG(i, regs) \ argument
331 if (i < ARRAY_SIZE(regs) && regs[i].reg > 0) { \
332 __assert_eq(regs[0].reg + i, regs[i].reg); \
333 if (regs[i].bo) { \
334 uint64_t v = regs[i].bo->iova + regs[i].bo_offset; \
335 v >>= regs[i].bo_shift; \
336 v |= regs[i].value; \
341 *p++ = regs[i].value; \
342 if (regs[i].is_address) \
343 *p++ = regs[i].value >> 32; \
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/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_pack.h55 const struct fd_reg_pair regs[] = {__VA_ARGS__}; \
57 if (i < ARRAY_SIZE(regs) && (i == 0 || regs[i].reg > 0)) { \
58 __assert_eq(regs[0].reg + i, regs[i].reg); \
59 if (regs[i].bo) { \
62 OUT_RELOC(ring, regs[i].bo, regs[i].bo_offset, regs[i].value, \
63 regs[i].bo_shift); \
65 *p++ = regs[i].value; \
66 if (regs[i].is_address) \
67 *p++ = regs[i].value >> 32; \
74 const struct fd_reg_pair regs[] = {__VA_ARGS__}; \
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/third_party/flutter/skia/third_party/externals/sdl/src/power/haiku/
DSDL_syspower.c48 uint16 regs[6]; in SDL_GetPowerInfo_Haiku() local
60 memset(regs, '\0', sizeof(regs)); in SDL_GetPowerInfo_Haiku()
61 regs[0] = APM_FUNC_OFFSET + APM_FUNC_GET_POWER_STATUS; in SDL_GetPowerInfo_Haiku()
62 regs[1] = APM_DEVICE_ALL; in SDL_GetPowerInfo_Haiku()
63 rc = ioctl(fd, APM_BIOS_CALL, regs); in SDL_GetPowerInfo_Haiku()
70 ac_status = regs[1] >> 8; in SDL_GetPowerInfo_Haiku()
71 battery_status = regs[1] & 0xFF; in SDL_GetPowerInfo_Haiku()
72 battery_flags = regs[2] >> 8; in SDL_GetPowerInfo_Haiku()
73 battery_life = regs[2] & 0xFF; in SDL_GetPowerInfo_Haiku()
74 battery_time = (uint32) regs[3]; in SDL_GetPowerInfo_Haiku()
/third_party/mesa3d/src/mesa/x86-64/
Dx86-64.c44 extern void _mesa_x86_64_cpuid(unsigned int *regs);
77 unsigned int regs[4]; in _mesa_init_all_x86_64_transform_asm() local
93 regs[0] = 0x80000001; in _mesa_init_all_x86_64_transform_asm()
94 regs[1] = 0x00000000; in _mesa_init_all_x86_64_transform_asm()
95 regs[2] = 0x00000000; in _mesa_init_all_x86_64_transform_asm()
96 regs[3] = 0x00000000; in _mesa_init_all_x86_64_transform_asm()
97 _mesa_x86_64_cpuid(regs); in _mesa_init_all_x86_64_transform_asm()
98 if (regs[3] & (1U << 31)) { in _mesa_init_all_x86_64_transform_asm()
/third_party/libunwind/src/sh/
DGresume.c43 unsigned long regs[8]; in sh_local_resume() local
44 regs[0] = uc->uc_mcontext.gregs[8]; in sh_local_resume()
45 regs[1] = uc->uc_mcontext.gregs[9]; in sh_local_resume()
46 regs[2] = uc->uc_mcontext.gregs[10]; in sh_local_resume()
47 regs[3] = uc->uc_mcontext.gregs[11]; in sh_local_resume()
48 regs[4] = uc->uc_mcontext.gregs[12]; in sh_local_resume()
49 regs[5] = uc->uc_mcontext.gregs[13]; in sh_local_resume()
50 regs[6] = uc->uc_mcontext.gregs[14]; in sh_local_resume()
51 regs[7] = uc->uc_mcontext.gregs[15]; in sh_local_resume()
55 char x[sizeof(regs)]; in sh_local_resume()
[all …]
/third_party/ltp/testcases/kernel/syscalls/ptrace/
Dptrace04.c31 } regs[] = { variable
65 for (i = 0; i < ARRAY_SIZE(regs); ++i) { in compare_registers()
68 (void *)regs[i].off, NULL); in compare_registers()
73 regs[i].name, regs[i].off); in compare_registers()
78 long *pt_val = (void *)&_pt_regs + regs[i].off; in compare_registers()
84 regs[i].name, regs[i].off, *pt_val, in compare_registers()
104 if (ARRAY_SIZE(regs) == 0) in main()
/third_party/boost/libs/beast/include/boost/beast/core/detail/
Dcpu_info.hpp48 int regs[4]; in cpuid() local
49 __cpuid(regs, id); in cpuid()
50 eax = regs[0]; in cpuid()
51 ebx = regs[1]; in cpuid()
52 ecx = regs[2]; in cpuid()
53 edx = regs[3]; in cpuid()
/third_party/boost/boost/beast/core/detail/
Dcpu_info.hpp48 int regs[4]; in cpuid() local
49 __cpuid(regs, id); in cpuid()
50 eax = regs[0]; in cpuid()
51 ebx = regs[1]; in cpuid()
52 ecx = regs[2]; in cpuid()
53 edx = regs[3]; in cpuid()
/third_party/mesa3d/src/gallium/frontends/nine/
Dnine_shader.c489 } regs; member
772 if (tx->num_scratch >= ARRAY_SIZE(tx->regs.t)) { in tx_scratch()
774 return tx->regs.t[0]; in tx_scratch()
776 if (ureg_dst_is_undef(tx->regs.t[tx->num_scratch])) in tx_scratch()
777 tx->regs.t[tx->num_scratch] = ureg_DECL_local_temporary(tx->ureg); in tx_scratch()
778 return tx->regs.t[tx->num_scratch++]; in tx_scratch()
804 tx->regs.r = REALLOC(tx->regs.r, in tx_temp_alloc()
805 k * sizeof(tx->regs.r[0]), in tx_temp_alloc()
806 n * sizeof(tx->regs.r[0])); in tx_temp_alloc()
808 tx->regs.r[k] = ureg_dst_undef(); in tx_temp_alloc()
[all …]
/third_party/flutter/skia/third_party/externals/zlib/
Dx86.c85 int regs[4]; in _x86_check_features() local
87 __cpuid(regs, 1); in _x86_check_features()
89 x86_cpu_has_sse2 = regs[3] & 0x4000000; in _x86_check_features()
90 x86_cpu_has_ssse3 = regs[2] & 0x000200; in _x86_check_features()
91 x86_cpu_has_sse42 = regs[2] & 0x100000; in _x86_check_features()
92 x86_cpu_has_pclmulqdq = regs[2] & 0x2; in _x86_check_features()
/third_party/node/deps/zlib/
Dx86.c85 int regs[4]; in _x86_check_features() local
87 __cpuid(regs, 1); in _x86_check_features()
89 x86_cpu_has_sse2 = regs[3] & 0x4000000; in _x86_check_features()
90 x86_cpu_has_ssse3 = regs[2] & 0x000200; in _x86_check_features()
91 x86_cpu_has_sse42 = regs[2] & 0x100000; in _x86_check_features()
92 x86_cpu_has_pclmulqdq = regs[2] & 0x2; in _x86_check_features()

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