| /third_party/mindspore/mindspore/ccsrc/backend/kernel_compiler/cpu/nnacl/intrinsics/avx/ |
| D | DeconvMatMulAvx.c | 25 __m256 res10 = _mm256_setzero_ps(); in Deconv4X8AvxKernel() local
38 res10 = _mm256_fmadd_ps(tmp3, w0, res10); in Deconv4X8AvxKernel()
44 _mm256_storeu_ps(dst + C24NUM, res10); in Deconv4X8AvxKernel()
54 __m256 res10 = _mm256_setzero_ps(); in Deconv4X16AvxKernel() local
72 res10 = _mm256_fmadd_ps(tmp3, w0, res10); in Deconv4X16AvxKernel()
79 _mm256_storeu_ps(dst + C24NUM, res10); in Deconv4X16AvxKernel()
97 __m256 res10 = _mm256_setzero_ps(); in Deconv4X24AvxKernel() local
118 res10 = _mm256_fmadd_ps(tmp, w0, res10); in Deconv4X24AvxKernel()
128 _mm256_storeu_ps(dst + C24NUM, res10); in Deconv4X24AvxKernel()
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| /third_party/skia/third_party/externals/spirv-cross/shaders-hlsl-no-opt/asm/frag/ |
| D | subgroup-arithmetic-cast.invalid.nofxc.sm60.asm.frag | 50 ;%res10 = OpGroupNonUniformUMin %uint %uint_3 ClusteredReduce %i %uint_4
62 ;OpStore %FragColor %res10
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| /third_party/skia/third_party/externals/spirv-cross/shaders-msl-no-opt/asm/frag/ |
| D | subgroup-arithmetic-cast.msl21.asm.frag | 50 %res10 = OpGroupNonUniformUMin %uint %uint_3 ClusteredReduce %i %uint_4
62 OpStore %FragColor %res10
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| /third_party/skia/third_party/externals/spirv-cross/shaders-no-opt/asm/frag/ |
| D | subgroup-arithmetic-cast.nocompat.vk.asm.frag | 50 %res10 = OpGroupNonUniformUMin %uint %uint_3 ClusteredReduce %i %uint_4
62 OpStore %FragColor %res10
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/crosstest/ |
| D | test_vector_ops_ll.ll | 165 %res10 = zext <16 x i1> %res10_i1 to <16 x i8>
166 ret <16 x i8> %res10
321 %res10 = insertelement <16 x i8> %vec, i8 %elt, i32 10
322 ret <16 x i8> %res10
509 %res10 = zext i1 %res10_i1 to i64
510 ret i64 %res10
685 %res10 = zext i8 %res10_i8 to i64
686 ret i64 %res10
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| /third_party/ffmpeg/libavcodec/ |
| D | cuviddec.c | 722 int res8 = 0, res10 = 0, res12 = 0; in cuvid_test_capabilities() local
749 res10 = CHECK_CU(ctx->cvdl->cuvidGetDecoderCaps(&ctx->caps10)); in cuvid_test_capabilities()
763 if (res10 < 0) in cuvid_test_capabilities()
764 return res10; in cuvid_test_capabilities()
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| /third_party/mesa3d/src/amd/compiler/tests/ |
| D | test_optimizer_postRA.cpp | 381 Temp res10 = bld.vop2(aco_opcode::v_add_f32, bld.def(v1, reg_v2), Operand(tmp10, reg_v2), b); variable
382 writeout(10, Operand(res10, reg_v2));
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| D | test_optimizer.cpp | 1044 Temp res10 = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), d, tmp10); variable
1045 writeout(10, res10);
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| /third_party/ffmpeg/libavcodec/mips/ |
| D | vp9_idct_msa.c | 1309 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vp9_iadst16_1d_columns_addblk_msa() local
1433 ILVR_B2_SH(zero, dst10, zero, dst11, res10, res11); in vp9_iadst16_1d_columns_addblk_msa()
1434 ADD2(res10, out10, res11, out11, res10, res11); in vp9_iadst16_1d_columns_addblk_msa()
1435 CLIP_SH2_0_255(res10, res11); in vp9_iadst16_1d_columns_addblk_msa()
1436 PCKEV_B2_SH(res10, res10, res11, res11, res10, res11); in vp9_iadst16_1d_columns_addblk_msa()
1437 ST_D1(res10, 0, dst + 6 * dst_stride); in vp9_iadst16_1d_columns_addblk_msa()
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| /third_party/mindspore/mindspore/ccsrc/backend/kernel_compiler/cpu/nnacl/fp32/ |
| D | matmul_fp32.c | 732 __m128 res10 = _mm_shuffle_ps(hi5, hi3, _MM_SHUFFLE(3, 2, 1, 0)); in RowMajor2Col6Major() local
744 _mm_storeu_ps(dst_c + 40, res10); in RowMajor2Col6Major()
|