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Searched refs:rmesa (Results 1 – 25 of 55) sorted by relevance

123

/third_party/mesa3d/src/mesa/drivers/dri/r200/
Dr200_cmdbuf.c55 void r200SetUpAtomList( r200ContextPtr rmesa ) in r200SetUpAtomList() argument
59 mtu = rmesa->radeon.glCtx.Const.MaxTextureUnits; in r200SetUpAtomList()
61 make_empty_list(&rmesa->radeon.hw.atomlist); in r200SetUpAtomList()
62 rmesa->radeon.hw.atomlist.name = "atom-list"; in r200SetUpAtomList()
64 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx ); in r200SetUpAtomList()
65 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.set ); in r200SetUpAtomList()
66 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin ); in r200SetUpAtomList()
67 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk ); in r200SetUpAtomList()
68 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt ); in r200SetUpAtomList()
69 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx ); in r200SetUpAtomList()
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Dr200_state.c72 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200AlphaFunc() local
73 int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC]; in r200AlphaFunc()
78 R200_STATECHANGE( rmesa, ctx ); in r200AlphaFunc()
110 rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc; in r200AlphaFunc()
116 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200BlendColor() local
117 R200_STATECHANGE( rmesa, ctx ); in r200BlendColor()
122 …rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3… in r200BlendColor()
207 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200_set_blend_state() local
208 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & in r200_set_blend_state()
218 R200_STATECHANGE( rmesa, ctx ); in r200_set_blend_state()
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Dr200_state_init.c167 static int cmdpkt( r200ContextPtr rmesa, int id ) in cmdpkt() argument
225 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
226 (void) rmesa; \
233 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
234 …return (!rmesa->radeon.TclFallback && !_mesa_arb_vertex_program_enabled(ctx) && (FLAG)) ? atom->cm…
240 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
241 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
247 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
249 …return (!rmesa->radeon.TclFallback && _mesa_arb_vertex_program_enabled(ctx) && (FLAG)) ? atom->cmd…
258 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !_mesa_ati_fragment_shader_enabled(c…
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Dradeon_dma.c141 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in rcommon_emit_vector() local
145 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); in rcommon_emit_vector()
149 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); in rcommon_emit_vector()
176 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in rcommon_emit_vecfog() local
183 radeonAllocDmaRegion( rmesa, &aos->bo, &aos->offset, size * 4, 32 ); in rcommon_emit_vecfog()
187 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); in rcommon_emit_vecfog()
205 void radeon_init_dma(radeonContextPtr rmesa) in radeon_init_dma() argument
207 make_empty_list(&rmesa->dma.free); in radeon_init_dma()
208 make_empty_list(&rmesa->dma.wait); in radeon_init_dma()
209 make_empty_list(&rmesa->dma.reserved); in radeon_init_dma()
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Dr200_tcl.c104 #define LOCAL_VARS r200ContextPtr rmesa = R200_CONTEXT(ctx)
123 R200_STATECHANGE( rmesa, lin ); \
124 radeonEmitState(&rmesa->radeon); \
128 R200_STATECHANGE( rmesa, lin ); \
130 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
133 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
135 radeonEmitState(&rmesa->radeon); \
139 #define ALLOC_ELTS(nr) r200AllocElts( rmesa, nr )
141 static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) in r200AllocElts() argument
143 if (rmesa->radeon.dma.flush == r200FlushElts && in r200AllocElts()
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Dr200_swtcl.c63 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
64 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
65 rmesa->radeon.swtcl.vertex_attr_count++; \
71 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
72 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
73 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
74 rmesa->radeon.swtcl.vertex_attr_count++; \
79 r200ContextPtr rmesa = R200_CONTEXT( ctx ); in r200SetVertexFormat() local
97 rmesa->radeon.swtcl.vertex_attr_count = 0; in r200SetVertexFormat()
102 if ( !rmesa->swtcl.needproj || in r200SetVertexFormat()
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Dr200_ioctl.h45 extern void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count);
46 extern void r200EmitVertexAOS( r200ContextPtr rmesa,
51 extern void r200EmitVbufPrim( r200ContextPtr rmesa,
57 extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
61 extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset);
65 void r200SetUpAtomList( r200ContextPtr rmesa );
73 #define R200_NEWPRIM( rmesa ) \ argument
75 if ( rmesa->radeon.dma.flush ) \
76 rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); \
82 #define R200_STATECHANGE( rmesa, ATOM ) \ argument
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Dr200_context.c75 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200GetString() local
78 GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 : in r200GetString()
79 rmesa->radeon.radeonScreen->AGPMode; in r200GetString()
89 !(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE) in r200GetString()
185 r200ContextPtr rmesa; in r200CreateContext() local
204 rmesa = align_calloc(sizeof(*rmesa), 16); in r200CreateContext()
205 if ( !rmesa ) { in r200CreateContext()
210 rmesa->radeon.radeonScreen = screen; in r200CreateContext()
211 r200_init_vtbl(&rmesa->radeon); in r200CreateContext()
219 driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache, in r200CreateContext()
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Dr200_texstate.c219 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200UpdateTextureEnv() local
224 GLuint color_scale = rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND2] & in r200UpdateTextureEnv()
227 GLuint alpha_scale = rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND2] & in r200UpdateTextureEnv()
242 color_scale |= ((rmesa->state.texture.unit[unit].outputreg + 1) << R200_TXC_OUTPUT_REG_SHIFT) | in r200UpdateTextureEnv()
245 alpha_scale |= ((rmesa->state.texture.unit[unit].outputreg + 1) << R200_TXA_OUTPUT_REG_SHIFT) | in r200UpdateTextureEnv()
313 [rmesa->state.texture.unit[replaceargs - 1].outputreg]; in r200UpdateTextureEnv()
338 [rmesa->state.texture.unit[unit - 1].outputreg]; in r200UpdateTextureEnv()
395 [rmesa->state.texture.unit[replaceargs - 1].outputreg]; in r200UpdateTextureEnv()
420 [rmesa->state.texture.unit[unit - 1].outputreg]; in r200UpdateTextureEnv()
624 if ( rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND] != color_combine || in r200UpdateTextureEnv()
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Dradeon_common.c106 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in radeonUpdateScissor() local
131 rmesa->state.scissor.rect.x1 = CLAMP(x1, min_x, max_x); in radeonUpdateScissor()
132 rmesa->state.scissor.rect.y1 = CLAMP(y1, min_y, max_y); in radeonUpdateScissor()
133 rmesa->state.scissor.rect.x2 = CLAMP(x2, min_x, max_x); in radeonUpdateScissor()
134 rmesa->state.scissor.rect.y2 = CLAMP(y2, min_y, max_y); in radeonUpdateScissor()
136 if (rmesa->vtbl.update_scissor) in radeonUpdateScissor()
137 rmesa->vtbl.update_scissor(ctx); in radeonUpdateScissor()
343 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); in radeonReadBuffer() local
344 radeon_update_renderbuffers(rmesa->driContext, in radeonReadBuffer()
345 rmesa->driContext->driReadablePriv, GL_FALSE); in radeonReadBuffer()
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Dr200_fragshader.c128 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200UpdateFSArith() local
133 R200_STATECHANGE( rmesa, afs[0] ); in r200UpdateFSArith()
134 R200_STATECHANGE( rmesa, afs[1] ); in r200UpdateFSArith()
137 afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; in r200UpdateFSArith()
140 afs_cmd = (GLuint *) rmesa->hw.afs[0].cmd; in r200UpdateFSArith()
322 afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; in r200UpdateFSArith()
324 rmesa->afs_loaded = ctx->ATIFragmentShader.Current; in r200UpdateFSArith()
328 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200UpdateFSRouting() local
332 R200_STATECHANGE( rmesa, ctx ); in r200UpdateFSRouting()
333 R200_STATECHANGE( rmesa, cst ); in r200UpdateFSRouting()
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Dr200_tex.c299 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200TexEnv() local
317 if ( rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] != envColor ) { in r200TexEnv()
318 R200_STATECHANGE( rmesa, tf ); in r200TexEnv()
319 rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] = envColor; in r200TexEnv()
335 min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ? in r200TexEnv()
341 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] & R200_LOD_BIAS_MASK) != b ) { in r200TexEnv()
342 R200_STATECHANGE( rmesa, tex[unit] ); in r200TexEnv()
343 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] &= ~R200_LOD_BIAS_MASK; in r200TexEnv()
344 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] |= b; in r200TexEnv()
350 R200_STATECHANGE( rmesa, spr ); in r200TexEnv()
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/third_party/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_ioctl.c62 void radeonSetUpAtomList( r100ContextPtr rmesa ) in radeonSetUpAtomList() argument
64 int i, mtu = rmesa->radeon.glCtx.Const.MaxTextureUnits; in radeonSetUpAtomList()
66 make_empty_list(&rmesa->radeon.hw.atomlist); in radeonSetUpAtomList()
67 rmesa->radeon.hw.atomlist.name = "atom-list"; in radeonSetUpAtomList()
69 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx); in radeonSetUpAtomList()
70 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set); in radeonSetUpAtomList()
71 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lin); in radeonSetUpAtomList()
72 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msk); in radeonSetUpAtomList()
73 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt); in radeonSetUpAtomList()
74 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl); in radeonSetUpAtomList()
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Dradeon_state.c69 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonAlphaFunc() local
70 int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC]; in radeonAlphaFunc()
75 RADEON_STATECHANGE( rmesa, ctx ); in radeonAlphaFunc()
107 rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc; in radeonAlphaFunc()
113 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonBlendEquationSeparate() local
114 GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~RADEON_COMB_FCN_MASK; in radeonBlendEquationSeparate()
137 FALLBACK( rmesa, RADEON_FALLBACK_BLEND_EQ, fallback ); in radeonBlendEquationSeparate()
139 RADEON_STATECHANGE( rmesa, ctx ); in radeonBlendEquationSeparate()
140 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b; in radeonBlendEquationSeparate()
143 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE; in radeonBlendEquationSeparate()
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Dradeon_dma.c141 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in rcommon_emit_vector() local
145 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); in rcommon_emit_vector()
149 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); in rcommon_emit_vector()
176 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in rcommon_emit_vecfog() local
183 radeonAllocDmaRegion( rmesa, &aos->bo, &aos->offset, size * 4, 32 ); in rcommon_emit_vecfog()
187 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); in rcommon_emit_vecfog()
205 void radeon_init_dma(radeonContextPtr rmesa) in radeon_init_dma() argument
207 make_empty_list(&rmesa->dma.free); in radeon_init_dma()
208 make_empty_list(&rmesa->dma.wait); in radeon_init_dma()
209 make_empty_list(&rmesa->dma.reserved); in radeon_init_dma()
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Dradeon_tcl.c109 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
115 #define GET_MESA_ELTS() rmesa->tcl.Elts
129 RADEON_STATECHANGE( rmesa, lin ); \
130 radeonEmitState(&rmesa->radeon); \
134 RADEON_STATECHANGE( rmesa, lin ); \
136 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
139 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
141 radeonEmitState(&rmesa->radeon); \
146 #define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr )
148 static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) in radeonAllocElts() argument
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Dradeon_swtcl.c67 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
68 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
69 rmesa->radeon.swtcl.vertex_attr_count++; \
75 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
76 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
77 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
78 rmesa->radeon.swtcl.vertex_attr_count++; \
90 r100ContextPtr rmesa = R100_CONTEXT( ctx ); in radeonSetVertexFormat() local
107 rmesa->radeon.swtcl.vertex_attr_count = 0; in radeonSetVertexFormat()
112 if ( !rmesa->swtcl.needproj || in radeonSetVertexFormat()
[all …]
Dradeon_state_init.c161 static int cmdpkt( r100ContextPtr rmesa, int id ) in cmdpkt() argument
197 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
198 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
510 void radeonInitState( r100ContextPtr rmesa ) in radeonInitState() argument
512 struct gl_context *ctx = &rmesa->radeon.glCtx; in radeonInitState()
515 rmesa->radeon.Fallback = 0; in radeonInitState()
518 rmesa->radeon.hw.max_state_size = 0; in radeonInitState()
522 rmesa->hw.ATOM.cmd_size = SZ; \ in radeonInitState()
523 rmesa->hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int)); \ in radeonInitState()
524 rmesa->hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int)); \ in radeonInitState()
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Dradeon_context.c97 r100ContextPtr rmesa = (r100ContextPtr)radeon; in r100_vtbl_pre_emit_state() local
100 rmesa->hw.zbs.dirty = 1; in r100_vtbl_pre_emit_state()
106 r100ContextPtr rmesa = R100_CONTEXT(ctx); in r100_vtbl_free_context() local
107 _mesa_vector4f_free( &rmesa->tcl.ObjClean ); in r100_vtbl_free_context()
150 r100ContextPtr rmesa; in r100CreateContext() local
169 rmesa = align_calloc(sizeof(*rmesa), 16); in r100CreateContext()
170 if ( !rmesa ) { in r100CreateContext()
175 rmesa->radeon.radeonScreen = screen; in r100CreateContext()
176 r100_init_vtbl(&rmesa->radeon); in r100CreateContext()
185 driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache, in r100CreateContext()
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Dradeon_texstate.c209 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonUpdateTextureEnv() local
235 rmesa->state.texture.unit[unit].format = 0; in radeonUpdateTextureEnv()
236 rmesa->state.texture.unit[unit].envMode = 0; in radeonUpdateTextureEnv()
535 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] != color_combine || in radeonUpdateTextureEnv()
536 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] != alpha_combine ) { in radeonUpdateTextureEnv()
537 RADEON_STATECHANGE( rmesa, tex[unit] ); in radeonUpdateTextureEnv()
538 rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] = color_combine; in radeonUpdateTextureEnv()
539 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] = alpha_combine; in radeonUpdateTextureEnv()
672 static void disable_tex_obj_state( r100ContextPtr rmesa, in disable_tex_obj_state() argument
675 RADEON_STATECHANGE( rmesa, tex[unit] ); in disable_tex_obj_state()
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Dradeon_ioctl.h42 extern void radeonEmitVertexAOS( r100ContextPtr rmesa,
47 extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
55 extern GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
61 extern void radeonEmitAOS( r100ContextPtr rmesa,
65 extern void radeonEmitBlit( r100ContextPtr rmesa,
75 extern void radeonEmitWait( r100ContextPtr rmesa, GLuint flags );
77 extern void radeonFlushCmdBuf( r100ContextPtr rmesa, const char * );
82 extern void radeonGetAllParams( r100ContextPtr rmesa );
83 extern void radeonSetUpAtomList( r100ContextPtr rmesa );
91 #define RADEON_NEWPRIM( rmesa ) \ argument
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Dradeon_common.c106 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in radeonUpdateScissor() local
131 rmesa->state.scissor.rect.x1 = CLAMP(x1, min_x, max_x); in radeonUpdateScissor()
132 rmesa->state.scissor.rect.y1 = CLAMP(y1, min_y, max_y); in radeonUpdateScissor()
133 rmesa->state.scissor.rect.x2 = CLAMP(x2, min_x, max_x); in radeonUpdateScissor()
134 rmesa->state.scissor.rect.y2 = CLAMP(y2, min_y, max_y); in radeonUpdateScissor()
136 if (rmesa->vtbl.update_scissor) in radeonUpdateScissor()
137 rmesa->vtbl.update_scissor(ctx); in radeonUpdateScissor()
343 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); in radeonReadBuffer() local
344 radeon_update_renderbuffers(rmesa->driContext, in radeonReadBuffer()
345 rmesa->driContext->driReadablePriv, GL_FALSE); in radeonReadBuffer()
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Dradeon_maos_arrays.c85 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in emit_tex_vector() local
100 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * 4, 32); in emit_tex_vector()
105 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * count * 4, 32); in emit_tex_vector()
145 r100ContextPtr rmesa = R100_CONTEXT( ctx ); in radeonEmitArrays() local
158 if (!rmesa->tcl.obj.buf) in radeonEmitArrays()
160 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
178 if (!rmesa->tcl.norm.buf) in radeonEmitArrays()
180 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
204 if (!rmesa->tcl.rgba.buf) in radeonEmitArrays()
206 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
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Dradeon_maos_verts.c312 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonEmitArrays() local
316 GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & in radeonEmitArrays()
360 if (((rmesa->NeedTexMatrix >> unit) & 1) && in radeonEmitArrays()
361 (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) in radeonEmitArrays()
362 radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; in radeonEmitArrays()
367 if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) { in radeonEmitArrays()
368 RADEON_STATECHANGE( rmesa, tcl ); in radeonEmitArrays()
369 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx; in radeonEmitArrays()
376 if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format && in radeonEmitArrays()
377 rmesa->radeon.tcl.aos[0].bo) in radeonEmitArrays()
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Dradeon_tex.c258 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonTexEnv() local
274 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] != envColor ) { in radeonTexEnv()
275 RADEON_STATECHANGE( rmesa, tex[unit] ); in radeonTexEnv()
276 rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] = envColor; in radeonTexEnv()
290 min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ? in radeonTexEnv()
300 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] & RADEON_LOD_BIAS_MASK) != b ) { in radeonTexEnv()
301 RADEON_STATECHANGE( rmesa, tex[unit] ); in radeonTexEnv()
302 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] &= ~RADEON_LOD_BIAS_MASK; in radeonTexEnv()
303 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] |= (b & RADEON_LOD_BIAS_MASK); in radeonTexEnv()
356 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonDeleteTexture() local
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