Home
last modified time | relevance | path

Searched refs:setRegClass (Results 1 – 25 of 27) sorted by relevance

12

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
142 setRegClass(Reg, NewRC); in recomputeRegClass()
DTailDuplicator.cpp420 MRI->setRegClass(VI->second.Reg, ConstrRC); in duplicateInstruction()
DMachineLICM.cpp1435 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]); in EliminateCSE()
DRegisterCoalescer.cpp1388 MRI->setRegClass(DstReg, NewRC); in reMaterializeTrivialDef()
1948 MRI->setRegClass(CP.getDstReg(), CP.getNewRC()); in joinCopy()
DModuloSchedule.cpp1890 MRI.setRegClass(R, MRI.getRegClass(PhiR)); in rewriteUsesOf()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp223 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
275 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
807 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
DAMDGPUInstructionSelector.cpp134 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
270 MRI->setRegClass(Src0.getReg(), RC); in selectG_AND_OR_XOR()
272 MRI->setRegClass(Src1.getReg(), RC); in selectG_AND_OR_XOR()
432 MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass); in selectG_UADDO_USUBO_UADDE_USUBE()
658 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC()
1157 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC_W_SIDE_EFFECTS()
1191 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
1611 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
DSILowerI1Copies.cpp571 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
692 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerCopiesToI1()
DAMDGPURegisterBankInfo.cpp912 MRI.setRegClass(UnmergePiece, &AMDGPU::VReg_64RegClass); in executeInWaterfallLoop()
913 MRI.setRegClass(CurrentLaneOpRegLo, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
914 MRI.setRegClass(CurrentLaneOpRegHi, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
931 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_64_XEXECRegClass); in executeInWaterfallLoop()
944 MRI.setRegClass(UnmergePiece, &AMDGPU::VGPR_32RegClass); in executeInWaterfallLoop()
945 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
DAMDGPULegalizerInfo.cpp1667 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass); in buildPCRelGlobalAddress()
2385 MRI.setRegClass(Def, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
2386 MRI.setRegClass(Use, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
2409 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp416 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1315 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1319 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1332 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1341 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2420 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2422 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
DPPCMIPeephole.cpp779 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
DPPCInstrInfo.cpp3849 MRI.setRegClass(RegToModify, NewRC); in transformToImmFormFedByLI()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceVariableSplitting.cpp106 NewVar->setRegClass(Var->getRegClass()); in makeLinked()
DIceTargetLoweringX8664.cpp2051 T_AhRcvr->setRegClass(RCX86_IsAhRcvr); in lowerArithmetic()
2129 T_AhRcvr->setRegClass(RCX86_IsAhRcvr); in lowerArithmetic()
2534 T_1->setRegClass(RCX86_Is32To8); in lowerCast()
2535 T_2->setRegClass(RCX86_IsTrunc8Rcvr); in lowerCast()
2563 T_1->setRegClass(RCX86_Is32To8); in lowerCast()
2564 T_2->setRegClass(RCX86_IsTrunc8Rcvr); in lowerCast()
3799 T_1->setRegClass(RCX86_Is32To8); in lowerIntrinsic()
3800 T_2->setRegClass(RCX86_IsTrunc8Rcvr); in lowerIntrinsic()
6543 Reg->setRegClass(RCX86_IsTrunc8Rcvr); in copyToReg8()
6548 SrcTruncable->setRegClass(RCX86_Is64To8); in copyToReg8()
[all …]
DIceTargetLoweringX8632.cpp2239 T_AhRcvr->setRegClass(RCX86_IsAhRcvr); in lowerArithmetic()
2313 T_AhRcvr->setRegClass(RCX86_IsAhRcvr); in lowerArithmetic()
2788 T_1->setRegClass(RCX86_Is32To8); in lowerCast()
2789 T_2->setRegClass(RCX86_IsTrunc8Rcvr); in lowerCast()
2813 T_1->setRegClass(RCX86_Is32To8); in lowerCast()
2814 T_2->setRegClass(RCX86_IsTrunc8Rcvr); in lowerCast()
4266 T_1->setRegClass(RCX86_Is32To8); in lowerIntrinsic()
4267 T_2->setRegClass(RCX86_IsTrunc8Rcvr); in lowerIntrinsic()
7281 Reg->setRegClass(RCX86_IsTrunc8Rcvr); in copyToReg8()
7286 SrcTruncable->setRegClass(RCX86_Is64To8); in copyToReg8()
[all …]
DIceOperand.h770 void setRegClass(uint8_t RC) { RegisterClass = static_cast<RegClass>(RC); } in setRegClass() function
DIceTargetLoweringARM32.cpp4062 TSrc0->setRegClass(RegARM32::RCARM32_QtoS); in lowerExtractElement()
4621 T->setRegClass(RegARM32::RCARM32_QtoS); in lowerInsertElement()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h670 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86DomainReassignment.cpp511 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); in reassign()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp146 MRI.setRegClass(Reg, &RC); in constrainGenericRegister()
DIRTranslator.cpp1173 MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF)); in getStackGuard()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstructionSelector.cpp481 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); in select()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/MIRParser/
DMIRParser.cpp598 MRI.setRegClass(Reg, Info.D.RC); in setupRegisterInfo()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp658 MRI->setRegClass(NewVReg, SRC); in EmitRegSequence()

12