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Searched refs:setne (Results 1 – 25 of 27) sorted by relevance

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/third_party/openssl/crypto/
Dx86cpuid.pl42 &setne (&LB("eax"));
45 &setne (&LB("eax"));
48 &setne (&LB("eax"));
53 &setne (&LB("eax"));
56 &setne (&LB("eax"));
59 &setne (&LB("eax"));
441 &setne ("dl");
Dx86_64cpuid.s54 setne %al
57 setne %al
60 setne %al
65 setne %al
68 setne %al
71 setne %al
385 setne %dl
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFloat.td90 def : Pat<(setne f32:$lhs, f32:$rhs), (NE_F32 f32:$lhs, f32:$rhs)>;
96 def : Pat<(setne f64:$lhs, f64:$rhs), (NE_F64 f64:$lhs, f64:$rhs)>;
113 // a setne with 0 into a select.
114 def : Pat<(select (i32 (setne I32:$cond, 0)), F32:$lhs, F32:$rhs),
116 def : Pat<(select (i32 (setne I32:$cond, 0)), F64:$lhs, F64:$rhs),
119 // And again, this time with seteq instead of setne and the arms reversed.
DWebAssemblyInstrInteger.td113 // a setne with 0 into a select.
114 def : Pat<(select (i32 (setne I32:$cond, 0)), I32:$lhs, I32:$rhs),
116 def : Pat<(select (i32 (setne I32:$cond, 0)), I64:$lhs, I64:$rhs),
119 // And again, this time with seteq instead of setne and the arms reversed.
DWebAssemblyInstrRef.td22 def : Pat<(select (i32 (setne I32:$cond, 0)), EXNREF:$lhs, EXNREF:$rhs),
DWebAssemblyInstrSIMD.td507 foreach nodes = [[seteq, EQ_v4f32], [setne, NE_v4f32], [setlt, LT_v4f32],
512 foreach nodes = [[seteq, EQ_v2f64], [setne, NE_v2f64], [setlt, LT_v2f64],
620 // Reductions already return 0 or 1, so and 1, setne 0, and seteq 1
630 def : Pat<(i32 (setne
DWebAssemblyInstrControl.td29 def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst),
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td217 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
225 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
248 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
252 def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
269 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
279 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
289 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
298 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
DMips64InstrInfo.td268 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>,
518 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
520 def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64,
570 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>, ASE_CNMIPS;
571 def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>, ASE_CNMIPS;
875 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
878 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
885 def : MipsPat<(brcond (i32 (setne (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst),
DMips16InstrInfo.td1486 // bcond-setne
1489 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1494 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1499 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1697 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1708 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1730 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1803 // setne
1806 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
DMipsCondMov.td97 def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
101 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
DMips32r6InstrInfo.td1042 def : MipsPat<(setne VT:$lhs, VT:$rhs),
1059 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, RC:$f),
1066 def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
1080 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, immz),
1084 def : MipsPat<(select (Opg (setne RC:$cond, immz)), immz, RC:$f),
DMicroMipsInstrInfo.td718 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
985 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
DMipsInstrInfo.td2223 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>,
3205 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
3245 def : MipsPat<(setne RC:$lhs, 0),
3249 def : MipsPat<(setne RC:$lhs, RC:$rhs),
DMicroMips32r6InstrInfo.td1811 def : MipsPat<(brcond (i32 (setne GPR32:$lhs, 0)), bb:$dst),
/third_party/ltp/tools/sparse/sparse-src/validation/backend/
Dcmp-ops.c6 static int setne(int x, int y) in setne() function
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPatterns.td663 def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)),
679 def: OpmR_RR_pat<Outn<C2_cmpeq>, setne, i1, I32>;
684 def: OpmR_RR_pat<Outn<C2_cmpeqp>, setne, i1, I64>;
689 def: OpmR_RR_pat<Outn<A2_vcmpbeq>, setne, v8i1, V8I8>;
694 def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>;
699 def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>;
708 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)),
712 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)),
747 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>;
758 def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))),
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreInstrInfo.td1171 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1184 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1186 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1198 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1212 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1214 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1243 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1252 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td850 def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>;
851 def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
852 def : Pat<(setne GPR:$rs1, simm12:$imm12),
880 def : BccPat<setne, BNE>;
DRISCVInstrInfoC.td473 def C_BNEZ : Bcz<0b111, "c.bnez", setne, GPRC>, Sched<[WriteJmp]>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1730 defm : ISET_FORMAT_SIGNED<setne, CmpNE>;
1739 def : Pat<(setne Int1Regs:$a, Int1Regs:$b),
1750 def : Pat<(i32 (setne Int1Regs:$a, Int1Regs:$b)),
1752 def : Pat<(i32 (setne Int1Regs:$a, Int1Regs:$b)),
1868 defm FSetNE : FSET_FORMAT<setne, CmpNE, CmpNE_FTZ>;
3076 // condition, 1', which will be translated to (setne condition, -1). Since ptx
3078 def : Pat<(brcond (i1 (setne Int1Regs:$a, -1)), bb:$target),
/third_party/mesa3d/src/mesa/x86/
Dassyntax.h628 #define SETNE(a) CHOICE(setne a, setne a, setne a)
1341 #define SETNE(a) setne a
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructions.td265 // for setne?
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DREADME.txt24 setne %dl
632 setne %al
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td1312 def setne : PatFrag<(ops node:$lhs, node:$rhs),

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