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Searched refs:sgpr (Results 1 – 25 of 33) sorted by relevance

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/third_party/mesa3d/src/amd/compiler/
Daco_live_var_analysis.cpp105 new_demand.sgpr -= phi_info[block->index].logical_phi_sgpr_ops; in process_live_temps_per_block()
114 register_demand[idx] = RegisterDemand(new_demand.vgpr, new_demand.sgpr); in process_live_temps_per_block()
138 new_demand.sgpr += phi_info[block->index].logical_phi_sgpr_ops; in process_live_temps_per_block()
203 assert(definition.getTemp().type() == RegType::sgpr); in process_live_temps_per_block()
249 if (insn->opcode == aco_opcode::p_phi && operand.getTemp().type() == RegType::sgpr) { in process_live_temps_per_block()
252 assert(operand.getTemp().type() == RegType::sgpr); in process_live_temps_per_block()
365 if (new_demand.vgpr > vgpr_limit || new_demand.sgpr > sgpr_limit) { in update_vgpr_sgpr_demand()
369 program->num_waves = program->dev.physical_sgprs / get_sgpr_alloc(program, new_demand.sgpr); in update_vgpr_sgpr_demand()
410 program->max_reg_demand.sgpr = get_addr_sgpr_from_waves(program, program->num_waves); in update_vgpr_sgpr_demand()
437 result.register_demand[block.index].back().sgpr += phi_info[block.index].linear_phi_defs; in live_var_analysis()
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Daco_validate.cpp303 check(instr->definitions[0].getTemp().type() == RegType::sgpr, in validate_ir()
311 unsigned sgpr[] = {0, 0}; in validate_ir() local
317 check(i != 1 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
329 check(i == 0 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
340 check(i == 2 || (op.isTemp() && op.regClass().type() == RegType::sgpr) || in validate_ir()
345 if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) { in validate_ir()
349 if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) { in validate_ir()
351 sgpr[num_sgprs++] = op.tempId(); in validate_ir()
364 check(instr->definitions[0].getTemp().type() == RegType::sgpr, in validate_ir()
367 check(op.isConstant() || op.regClass().type() <= RegType::sgpr, in validate_ir()
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Daco_ir.h302 sgpr, enumerator
346 constexpr RegType type() const { return rc <= RC::s16 ? RegType::sgpr : RegType::vgpr; } in type()
358 if (type == RegType::sgpr) { in get()
1807 constexpr RegisterDemand(const int16_t v, const int16_t s) noexcept : vgpr{v}, sgpr{s} {} in RegisterDemand()
1809 int16_t sgpr = 0; member
1813 return a.vgpr == b.vgpr && a.sgpr == b.sgpr;
1818 return vgpr > other.vgpr || sgpr > other.sgpr; in exceeds()
1823 if (t.type() == RegType::sgpr)
1824 return RegisterDemand(vgpr, sgpr + t.size());
1826 return RegisterDemand(vgpr + t.size(), sgpr);
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Daco_spill.cpp472 reg_pressure.sgpr = in get_live_in_demand()
473 std::max<int16_t>(reg_pressure.sgpr, ctx.register_demand[pred].back().sgpr); in get_live_in_demand()
528 type = RegType::sgpr; in init_live_in_vars()
530 if (type == RegType::sgpr && loop_demand.sgpr <= ctx.target_pressure.sgpr) in init_live_in_vars()
539 (ctx.remat.count(pair.first) && type == RegType::sgpr)) && in init_live_in_vars()
548 if (type == RegType::sgpr) in init_live_in_vars()
550 type = RegType::sgpr; in init_live_in_vars()
576 type = reg_pressure.vgpr > ctx.target_pressure.vgpr ? RegType::vgpr : RegType::sgpr; in init_live_in_vars()
600 if (pair.first.type() != RegType::sgpr) { in init_live_in_vars()
607 spilled_registers.sgpr += pair.first.size(); in init_live_in_vars()
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Daco_instruction_selection_setup.cpp244 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components); in get_reg_class()
465 nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr; in init_context()
567 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
575 RegType type = RegType::sgpr; in init_context()
611 case nir_intrinsic_load_viewport_y_offset: type = RegType::sgpr; break; in init_context()
728 type = nir_dest_is_divergent(intrinsic->dest) ? RegType::vgpr : RegType::sgpr; in init_context()
731 type = ctx->stage == fragment_fs ? RegType::vgpr : RegType::sgpr; in init_context()
748 RegType type = nir_dest_is_divergent(tex->dest) ? RegType::vgpr : RegType::sgpr; in init_context()
768 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); in init_context()
774 RegType type = RegType::sgpr; in init_context()
Daco_optimizer.cpp530 if (temp.type() == RegType::sgpr && !can_accept_sgpr) in pseudo_propagate_temp()
534 if (temp.type() == RegType::sgpr && !can_accept_sgpr) in pseudo_propagate_temp()
667 unsigned sgpr[] = {0, 0}; in check_vop3_operands() local
672 if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) { in check_vop3_operands()
674 if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) { in check_vop3_operands()
676 sgpr[num_sgprs++] = op.tempId(); in check_vop3_operands()
900 op.getTemp().type() == RegType::sgpr)) { in check_sdwa_extract()
1019 if (info.is_temp() && info.temp.type() == RegType::sgpr && can_apply_sgprs(ctx, instr) && in label_instruction()
1808 if (op[1].type() == RegType::sgpr) in combine_ordering_test()
1810 unsigned num_sgprs = (op[0].type() == RegType::sgpr) + (op[1].type() == RegType::sgpr); in combine_ordering_test()
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Daco_register_allocation.cpp189 return {PhysReg{0}, (unsigned)program->max_reg_demand.sgpr}; in get_reg_bounds()
397 PhysRegInterval regs = get_reg_bounds(ctx.program, vgprs ? RegType::vgpr : RegType::sgpr); in print_regs()
1318 if (rc.type() == RegType::sgpr && reg % get_stride(rc) != 0) in get_reg_specified()
1325 bool is_vcc = rc.type() == RegType::sgpr && vcc_win.contains(reg_win); in get_reg_specified()
1349 ctx.program->max_reg_demand.sgpr)); in increase_register_file()
1350 } else if (type == RegType::sgpr && ctx.program->max_reg_demand.sgpr < ctx.sgpr_limit) { in increase_register_file()
1352 ctx.program->max_reg_demand.sgpr + 1)); in increase_register_file()
1821 for (; reg < ctx.program->max_reg_demand.sgpr && reg_file[PhysReg{(unsigned)reg}]; reg++) in handle_pseudo()
1823 if (reg == ctx.program->max_reg_demand.sgpr) { in handle_pseudo()
2487 phi->operands[idx].getTemp().type() == RegType::sgpr && in register_allocation()
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Daco_insert_NOPs.cpp412 if (def.regClass().type() != RegType::sgpr) { in handle_instruction_gfx6()
443 if (!op.isConstant() && !op.isUndefined() && op.regClass().type() == RegType::sgpr) in handle_instruction_gfx6()
504 if (def.regClass().type() == RegType::sgpr) { in handle_instruction_gfx6()
612 { return def.getTemp().type() == RegType::sgpr; }); in instr_writes_sgpr()
Daco_instruction_selection.cpp270 if (val.type() == RegType::sgpr) { in as_vgpr()
354 assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr); in emit_extract_vector()
381 if (vec_src.type() == RegType::sgpr) { in emit_split_vector()
415 if (dst.type() == RegType::sgpr) in expand_vector()
433 if (dst.type() == RegType::sgpr) in expand_vector()
555 vec = bld.pseudo(aco_opcode::p_as_uniform, bld.def(RegClass(RegType::sgpr, vec.size())), vec); in byte_align_vector()
612 if (dst_bits % 32 == 0 || src.type() == RegType::sgpr) in convert_int()
618 assert(src.type() == RegType::sgpr || src_bits == src.bytes() * 8); in convert_int()
619 assert(dst.type() == RegType::sgpr || dst_bits == dst.bytes() * 8); in convert_int()
715 if (elem_size < 4 && vec.type() == RegType::sgpr && size == 1) { in get_alu_src()
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Daco_lower_to_cssa.cpp103 if (def.regClass().type() == RegType::sgpr && !op.isTemp()) { in collect_parallelcopies()
500 emit_copies_block(bld, ltg, RegType::sgpr); in emit_parallelcopies()
Daco_print_ir.cpp94 } else if (rc.type() == RegType::sgpr) { in print_reg_class()
825 fprintf(output, "\tdemand: %u vgpr, %u sgpr\n", demand.vgpr, demand.sgpr); in aco_print_block()
833 fprintf(output, "(%3u vgpr, %3u sgpr) ", demand.vgpr, demand.sgpr); in aco_print_block()
Daco_ir.cpp284 if (instr->definitions[0].getTemp().type() == RegType::sgpr && chip == GFX8) in convert_to_SDWA()
680 (instr->operands[0].isTemp() && instr->operands[0].getTemp().type() == RegType::sgpr)) in can_swap_operands()
Daco_lower_to_hw_instr.cpp433 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size)); in emit_op()
827 if (dst.regClass().type() == RegType::sgpr) { in emit_reduction()
1529 it->second.op.regClass().type() == RegType::sgpr ? s2 : v2); in handle_operands()
1531 it->second.def.regClass().type() == RegType::sgpr ? s2 : v2); in handle_operands()
1767 if (preserve_scc && it->second.def.getTemp().type() == RegType::sgpr) in handle_operands()
2072 instr->operands[0].regClass().type() == RegType::sgpr) { in lower_to_hw_instr()
2079 assert(instr->definitions[0].regClass().type() == RegType::sgpr); in lower_to_hw_instr()
Daco_lower_phis.cpp325 assert(phi_src.regClass().type() == RegType::sgpr); in lower_subdword_phis()
Daco_optimizer_postRA.cpp91 assert(def.regClass().type() != RegType::sgpr || def.physReg().reg() <= 255); in save_reg_writes()
Daco_statistics.cpp43 program->statistics[statistic_sgpr_presched] = presched_demand.sgpr; in collect_presched_stats()
DREADME.md279 …Typical issues might be a wrong instruction format leading to a wrong opcode or an sgpr used for v…
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUGenRegisterBankInfo.def137 /*32-bit sgpr*/ {&SGPROnly64BreakDown[0], 1},
138 /*2 x 32-bit sgpr*/ {&SGPROnly64BreakDown[1], 2},
139 /*64-bit sgpr */ {&SGPROnly64BreakDown[3], 1},
DAMDGPU.td145 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
/third_party/mesa3d/docs/relnotes/
D19.3.4.rst179 - aco: fix target calculation when vgpr spilling introduces sgpr
D17.3.4.rst95 - ac/nir: account for view index in the user sgpr allocation.
/third_party/mesa3d/src/amd/llvm/
Dac_llvm_build.h178 void ac_build_optimization_barrier(struct ac_llvm_context *ctx, LLVMValueRef *pgpr, bool sgpr);
Dac_llvm_build.c404 void ac_build_optimization_barrier(struct ac_llvm_context *ctx, LLVMValueRef *pgpr, bool sgpr) in ac_build_optimization_barrier() argument
410 const char *constraint = sgpr ? "=s,0" : "=v,0"; in ac_build_optimization_barrier()
/third_party/mesa3d/src/amd/compiler/tests/
Dtest_sdwa.cpp334 BEGIN_TEST(optimize.sdwa.extract.sgpr)
Dhelpers.cpp119 …RegClass cls(input_spec[i * 3] == 'v' ? RegType::vgpr : RegType::sgpr, input_spec[i * 3 + 1] - '0'… in setup_cs()

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