| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SOPInstructions.td | 642 bits<16> simm16;
649 let Inst{15-0} = simm16;
658 let Inst{15-0} = simm16;
673 (ins s16imm:$simm16),
674 "$sdst, $simm16",
680 (ins sopp_brtarget:$simm16, SReg_32:$sdst),
681 "$sdst, $simm16",
694 (ins SReg_32:$sdst, s16imm:$simm16),
695 (ins SReg_32:$sdst, u16imm:$simm16)),
696 "$sdst, $simm16", []>,
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| D | SIModeRegister.cpp | 245 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); in processBlockPhase1()
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| D | GCNHazardRecognizer.cpp | 127 AMDGPU::OpName::simm16); in getHWReg()
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| D | SIInstructions.td | 330 def SI_BR_UNDEF : SPseudoInstSI <(outs), (ins sopp_brtarget:$simm16)> {
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| D | SIInstrInfo.cpp | 3556 auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16); in verifyInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 23 let MIOperandInfo = (ops CPU16Regs, simm16);
35 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
41 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
64 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
82 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
96 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
105 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
121 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
160 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
193 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
[all …]
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| D | MipsInstrInfo.td | 959 // Like uimm16_64 but coerces simm16 to uimm16.
979 // Like uimm16_64 but coerces simm16 to uimm16.
1057 // Like simm16 but coerces uimm16 to simm16.
1124 let MIOperandInfo = (ops ptr_rc, simm16);
1169 let MIOperandInfo = (ops ptr_rc, simm16);
1670 InstSE<(outs), (ins RO:$rs, simm16:$imm16),
2038 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
2040 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
2528 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
2533 (ROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>;
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| D | MicroMipsInstrInfo.td | 141 let MIOperandInfo = (ops ptr_rc, simm16);
722 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
724 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
726 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
728 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
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| D | MicroMips32r6InstrInfo.td | 345 : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
540 dag InOperandList = (ins simm16:$imm);
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| D | Mips32r6InstrInfo.td | 344 dag InOperandList = (ins simm16:$imm);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenInstrInfo.inc | 10680 simm16 = 73,
13924 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13926 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13927 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13930 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13932 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13933 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget,
13948 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16,
13950 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16,
13968 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::simm16,
[all …]
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| /third_party/mesa3d/docs/relnotes/ |
| D | 13.0.3.rst | 115 - radeonsi: allow specifying simm16 of emit_waitcnt at call sites
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| /third_party/mesa3d/src/amd/llvm/ |
| D | ac_llvm_build.c | 2489 unsigned simm16 = (lgkmcnt << 8) | (7 << 4) | /* expcnt */ in ac_build_waitcnt() local
2493 LLVMConstInt(ctx->i32, simm16, false), in ac_build_waitcnt()
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