| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_insert_waitcnt.cpp | 376 if (ctx.pending_s_buffer_store && !instr->smem().definitions.empty() && in kill()
377 !instr->smem().sync.can_reorder()) { in kill()
647 SMEM_instruction& smem = instr->smem(); in gen() local
648 update_counters(ctx, event_smem, smem.sync); in gen()
652 else if (ctx.chip_class >= GFX10 && !smem.sync.can_reorder()) in gen()
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| D | aco_print_ir.cpp | 338 const SMEM_instruction& smem = instr->smem(); in print_instr_format_specific() local
339 if (smem.glc) in print_instr_format_specific()
341 if (smem.dlc) in print_instr_format_specific()
343 if (smem.nv) in print_instr_format_specific()
345 print_sync(smem.sync, output); in print_instr_format_specific()
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| D | aco_assembler.cpp | 181 SMEM_instruction& smem = instr->smem(); in emit_instruction() local
211 assert(!smem.dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
212 encoding |= smem.nv ? 1 << 15 : 0; in emit_instruction()
215 assert(!smem.nv); /* Non-volatile is not supported on GFX10 */ in emit_instruction()
216 encoding |= smem.dlc ? 1 << 14 : 0; in emit_instruction()
220 encoding |= smem.glc ? 1 << 16 : 0; in emit_instruction()
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| D | aco_optimizer.cpp | 1180 SMEM_instruction& smem = instr->smem(); in label_instruction() local
1183 bool prevent_overflow = smem.operands[0].size() > 2 || smem.prevent_overflow; in label_instruction()
1193 bool soe = smem.operands.size() >= (!smem.definitions.empty() ? 3 : 4); in label_instruction()
1194 if (soe && (!ctx.info[smem.operands.back().tempId()].is_constant_or_literal(32) || in label_instruction()
1195 ctx.info[smem.operands.back().tempId()].val != 0)) { in label_instruction()
1199 smem.operands[1] = Operand::c32(offset); in label_instruction()
1200 smem.operands.back() = Operand(base); in label_instruction()
1203 smem.opcode, Format::SMEM, smem.operands.size() + 1, smem.definitions.size()); in label_instruction()
1204 new_instr->operands[0] = smem.operands[0]; in label_instruction()
1206 if (smem.definitions.empty()) in label_instruction()
[all …]
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| D | aco_statistics.cpp | 134 case instr_class::smem: return {0, WAIT_USE(scalar, 1)}; in get_perf_info()
162 case instr_class::smem: return {4, WAIT_USE(scalar, 4)}; in get_perf_info()
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| D | aco_opt_value_numbering.cpp | 203 SMEM_instruction& aS = a->smem(); in operator ()()
204 SMEM_instruction& bS = b->smem(); in operator ()()
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| D | aco_ir.h | 121 smem = 11, enumerator
1087 SMEM_instruction& smem() noexcept in smem() function
1092 const SMEM_instruction& smem() const noexcept in smem() function
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| D | aco_instruction_selection.cpp | 4441 split_buffer_store(isel_context* ctx, nir_intrinsic_instr* instr, bool smem, RegType dst_type, in split_buffer_store() argument
4469 if ((ctx->program->chip_class == GFX6 || smem) && byte == 12) in split_buffer_store()
5071 Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off); in visit_load_input()
5366 return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off); //, false, false, false); in load_desc_ptr()
5462 return bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), set_ptr, binding); in load_buffer_rsrc()
5520 bld.smem(aco_opcode::s_load_dwordx4, Definition(dst), desc_base, desc_off); in visit_load_sbt_amd()
5592 bld.smem(op, Definition(vec), ptr, index).instr->smem().prevent_overflow = true; in visit_load_push_constant()
5872 Temp res = bld.smem(opcode, bld.def(type), list, off); in get_sampler_desc()
7272 bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand::zero()); in get_scratch_resource()
7378 bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, in visit_emit_vertex_with_counter()
[all …]
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| D | aco_ir.cpp | 172 case Format::SMEM: return instr->smem().sync; in get_sync_info()
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| D | aco_spill.cpp | 1407 bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, Operand::zero()); in load_scratch_resource()
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| /third_party/mesa3d/src/amd/compiler/tests/ |
| D | test_hard_clause.cpp | 87 bld.smem(aco_opcode::s_load_dword, Definition(PhysReg(0), s1), Operand(PhysReg(0), s2), in create_smem()
95 bld.smem(aco_opcode::s_buffer_load_dword, Definition(PhysReg(0), s1), desc_op, Operand::zero()); in create_smem_buffer()
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| D | test_assembler.cpp | 37 bld.smem(aco_opcode::s_memtime, bld.def(s2)).def(0).setFixed(PhysReg{0});
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| /third_party/mesa3d/src/panfrost/lib/genxml/ |
| D | decode.c | 267 struct pandecode_mapped_memory *smem = in pandecode_sample_locations() local
270 const u16 *PANDECODE_PTR_VAR(samples, smem, params.sample_locations); in pandecode_sample_locations()
824 … struct pandecode_mapped_memory *smem = pandecode_find_mapped_gpu_mem_containing(p->state); in pandecode_dcd() local
825 uint32_t *cl = pandecode_fetch_gpu_mem(smem, p->state, pan_size(RENDERER_STATE)); in pandecode_dcd()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.1.6.rst | 110 - nv50/ir/nir: fix smem size for GL
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| D | 13.0.4.rst | 117 - radv: flush smem for uniform buffer bit.
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| D | 20.1.0.rst | 3545 - aco: add vmem/smem score statistic
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| D | 21.3.0.rst | 2325 - nv50/ir/nir: fix smem size for GL
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| D | 20.2.0.rst | 3920 - aco: improve workgroup-scope and lower vmem/smem barriers
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| D | 20.3.0.rst | 3081 - nv50/ir/nir: fix smem size
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| D | 21.2.0.rst | 3225 - nv50/ir/nir: fix smem size for GL
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| D | 21.1.0.rst | 4788 - aco: remove vmem/smem score statistics
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_clear.c | 476 const uint32_t smem = 0; in si_get_htile_clear_value() local
513 ((smem & 0x3) << 8) | in si_get_htile_clear_value()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_meta_clear.c | 876 uint32_t zmask = 0, smem = 0; in radv_get_htile_fast_clear_value() local
915 ((smem & 0x3) << 8) | in radv_get_htile_fast_clear_value()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPU.td | 175 def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
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