| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_lower_to_hw_instr.cpp | 488 bld.sop1(Builder::s_or_saveexec, Definition(stmp, bld.lm), Definition(scc, s1), in emit_reduction()
496 bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg{sitmp + i}, s1), identity[i]); in emit_reduction()
649 bld.sop1(aco_opcode::s_mov_b32, Definition(exec_lo, s1), Operand::c32(0x10000u)); in emit_reduction()
650 bld.sop1(aco_opcode::s_mov_b32, Definition(exec_hi, s1), Operand::c32(0x10000u)); in emit_reduction()
659 bld.sop1(Builder::s_mov, Definition(exec, bld.lm), Operand::c64(UINT64_MAX)); in emit_reduction()
679 bld.sop1(aco_opcode::s_mov_b32, Definition(exec_lo, s1), Operand::c32(0x10101010u)); in emit_reduction()
680 bld.sop1(aco_opcode::s_mov_b32, Definition(exec_hi, s1), Operand(exec_lo, s1)); in emit_reduction()
685 bld.sop1(aco_opcode::s_mov_b64, Definition(exec, s2), Operand::c64(UINT64_MAX)); in emit_reduction()
688 bld.sop1(aco_opcode::s_mov_b32, Definition(exec_lo, s1), Operand::c32(0x01000100u)); in emit_reduction()
689 bld.sop1(aco_opcode::s_mov_b32, Definition(exec_hi, s1), Operand(exec_lo, s1)); in emit_reduction()
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| D | aco_insert_exec_mask.cpp | 359 exec_mask = bld.sop1(Builder::s_wqm, Definition(exec, bld.lm), bld.def(s1, scc), in transition_to_WQM()
394 wqm = bld.sop1(Builder::s_and_saveexec, bld.def(bld.lm), bld.def(s1, scc), in transition_to_Exact()
433 bld.sop1(Builder::s_wqm, Definition(exec, bld.lm), bld.def(s1, scc), in add_coupling_code()
782 bld.sop1(Builder::s_and_saveexec, bld.def(bld.lm), bld.scc(Definition(exit_cond)), in process_instructions()
824 Temp first_lane_idx = bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)); in process_instructions()
940 Temp cond = bld.sop1(Builder::s_and_saveexec, bld.def(bld.lm), bld.def(s1, scc), in add_branch_code()
1015 Temp old_exec = bld.sop1(Builder::s_and_saveexec, bld.def(bld.lm), bld.def(s1, scc), in add_branch_code()
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| D | aco_assembler.cpp | 891 instr.reset(bld.sop1(aco_opcode::s_getpc_b64, branch->definitions[0]).instr); in emit_long_jump()
907 instr.reset(bld.sop1(aco_opcode::s_bitset0_b32, def_tmp_lo, Operand::zero()).instr); in emit_long_jump()
912 bld.sop1(aco_opcode::s_setpc_b64, Operand(branch->definitions[0].physReg(), s2)).instr); in emit_long_jump()
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| D | aco_instruction_selection.cpp | 212 Temp index_is_lo_n1 = bld.sop1(aco_opcode::s_not_b32, bld.def(s1), bld.def(s1, scc), in emit_bpermute()
1438 bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src); in visit_alu_instr()
1447 bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), src); in visit_alu_instr()
1675 bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src); in visit_alu_instr()
1679 bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src); in visit_alu_instr()
1694 Temp msb_rev = bld.sop1(op, bld.def(s1), src); in visit_alu_instr()
1737 bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0])); in visit_alu_instr()
2405 Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), in visit_alu_instr()
2877 Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand::c32(0xfffffffeu)); in visit_alu_instr()
3463 bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src); in visit_alu_instr()
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| D | aco_ir.h | 1032 SOP1_instruction& sop1() noexcept in sop1() function
1037 const SOP1_instruction& sop1() const noexcept in sop1() function
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| /third_party/mesa3d/src/amd/compiler/tests/ |
| D | test_assembler.cpp | 223 bld.sop1(aco_opcode::p_constaddr_getpc, Definition(PhysReg(0), s2), Operand::zero());
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| D | test_optimizer_postRA.cpp | 71 auto ovrwr = bld.sop1(Builder::s_mov, bld.def(bld.lm, vcc), Operand::zero());
121 auto ovrwr = bld.sop1(Builder::s_mov, bld.def(bld.lm, exec), Operand::c32(42u));
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