| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 131 static struct rc_src_register srcreg(int file, int index) in srcreg() function
255 inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index)); in transform_CEIL()
271 srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[1]); in transform_CLAMP()
320 inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, dst.Index))); in transform_FLR()
336 negate(srcreg(RC_FILE_TEMPORARY, dst.Index))); in transform_TRUNC()
338 negate(srcreg(RC_FILE_TEMPORARY, dst.Index)), srcreg(RC_FILE_TEMPORARY, dst.Index)); in transform_TRUNC()
375 srcreg(RC_FILE_TEMPORARY, rc_find_free_temporary(c))); in transform_LIT()
383 srctemp = srcreg(RC_FILE_TEMPORARY, temp); in transform_LIT()
391 swizzle(srcreg(RC_FILE_CONSTANT, constant), in transform_LIT()
435 inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[2]); in transform_LRP()
[all …]
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| D | radeon_compiler_util.c | 288 struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register srcreg) in lmul_swizzle() argument
290 struct rc_src_register tmp = srcreg; in lmul_swizzle()
297 tmp.Swizzle |= GET_SWZ(srcreg.Swizzle, swz) << (i*3); in lmul_swizzle()
298 tmp.Negate |= GET_BIT(srcreg.Negate, swz) << i; in lmul_swizzle()
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| D | radeon_compiler_util.h | 73 struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register srcreg);
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| /third_party/mesa3d/src/gallium/drivers/svga/svgadump/ |
| D | svga_shader_dump.c | 420 static void dump_srcreg( struct sh_srcreg srcreg, struct sh_srcreg *indreg, const struct dump_info … in dump_srcreg() argument
425 memcpy(&srcreg_sh, &srcreg, sizeof(srcreg_sh)); in dump_srcreg()
427 switch (srcreg.modifier) { in dump_srcreg()
442 switch (srcreg.modifier) { in dump_srcreg()
473 …if (srcreg.swizzle_x != 0 || srcreg.swizzle_y != 1 || srcreg.swizzle_z != 2 || srcreg.swizzle_w !=… in dump_srcreg()
475 …if (srcreg.swizzle_x == srcreg.swizzle_y && srcreg.swizzle_y == srcreg.swizzle_z && srcreg.swizzle… in dump_srcreg()
476 _debug_printf( "%c", "xyzw"[srcreg.swizzle_x] ); in dump_srcreg()
479 _debug_printf( "%c", "xyzw"[srcreg.swizzle_x] ); in dump_srcreg()
480 _debug_printf( "%c", "xyzw"[srcreg.swizzle_y] ); in dump_srcreg()
481 _debug_printf( "%c", "xyzw"[srcreg.swizzle_z] ); in dump_srcreg()
[all …]
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| /third_party/mesa3d/src/gallium/frontends/d3d10umd/ |
| D | ShaderTGSI.c | 1411 struct ureg_src srcreg[2]; in Shader_tgsi_translate() local
1412 srcreg[0] = translate_src_operand(&sx, &opcode.src[0], OF_INT); in Shader_tgsi_translate()
1413 srcreg[1] = translate_src_operand(&sx, &opcode.src[1], OF_INT); in Shader_tgsi_translate()
1418 srcreg); in Shader_tgsi_translate()
1530 struct ureg_src srcreg[3]; in Shader_tgsi_translate() local
1531 srcreg[0] = translate_src_operand(&sx, &opcode.src[0], OF_FLOAT); in Shader_tgsi_translate()
1532 srcreg[1] = translate_src_operand(&sx, &opcode.src[1], OF_UINT); in Shader_tgsi_translate()
1533 srcreg[2] = translate_src_operand(&sx, &opcode.src[2], OF_UINT); in Shader_tgsi_translate()
1538 srcreg); in Shader_tgsi_translate()
1579 struct ureg_src srcreg[4]; in Shader_tgsi_translate() local
[all …]
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| /third_party/mesa3d/src/intel/isl/ |
| D | isl_tiled_memcpy.c | 127 __m128i srcreg, dstreg, agmask, ag, rb, br; in rgba8_copy_16_aligned_dst() local
130 srcreg = _mm_loadu_si128((__m128i *)src); in rgba8_copy_16_aligned_dst()
132 rb = _mm_andnot_si128(agmask, srcreg); in rgba8_copy_16_aligned_dst()
133 ag = _mm_and_si128(agmask, srcreg); in rgba8_copy_16_aligned_dst()
144 __m128i srcreg, dstreg, agmask, ag, rb, br; in rgba8_copy_16_aligned_src() local
147 srcreg = _mm_load_si128((__m128i *)src); in rgba8_copy_16_aligned_src()
149 rb = _mm_andnot_si128(agmask, srcreg); in rgba8_copy_16_aligned_src()
150 ag = _mm_and_si128(agmask, srcreg); in rgba8_copy_16_aligned_src()
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| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_compiler_tgsi.c | 1885 const struct etna_reg_desc *srcreg = etna_get_src_reg(c, reg->Register); in etna_compile_pass_generate_code() local
1886 const struct etna_native_reg *n = &srcreg->native; in etna_compile_pass_generate_code()
1897 if (srcreg && srcreg->has_semantic && in etna_compile_pass_generate_code()
1898 srcreg->semantic.Name == TGSI_SEMANTIC_TEXCOORD && in etna_compile_pass_generate_code()
1899 (c->key->sprite_coord_enable & BITFIELD_BIT(srcreg->semantic.Index))) { in etna_compile_pass_generate_code()
1903 .dst = etna_native_to_dst(srcreg->native, INST_COMPS_W), in etna_compile_pass_generate_code()
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| /third_party/mesa3d/src/freedreno/decode/ |
| D | cffdec.c | 1786 uint32_t srcreg = dwords[1]; in cp_set_const() local
1791 assert(srcreg < ARRAY_SIZE(type0_reg_vals)); in cp_set_const()
1797 printf("%s (%08x)\n", regname(srcreg, 1), type0_reg_vals[srcreg]); in cp_set_const()
1799 dstval += type0_reg_vals[srcreg]; in cp_set_const()
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| /third_party/mesa3d/docs/drivers/freedreno/ |
| D | ir3-notes.rst | 119 ``foreach_src(srcreg, instr)``
122 ``foreach_src_n(srcreg, n, instr)``
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoD.td | 77 // Operands for stores are in the order srcreg, base, offset rather than
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| D | RISCVInstrInfoF.td | 111 // Operands for stores are in the order srcreg, base, offset rather than
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| D | RISCVInstrInfo.td | 312 // Operands for stores are in the order srcreg, base, offset rather than
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