Searched refs:srsrc (Results 1 – 12 of 12) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | BUFInstructions.td | 129 bits<7> srsrc; 143 (ins SReg_128:$srsrc, SCSrc_b32:$soffset, 145 (ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset, 149 (ins vdataClass:$vdata, SReg_128:$srsrc, 152 (ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc, 171 !if(!eq(addrKind, BUFAddrKind.Offset), "off, $srsrc, $format, $soffset", 173 "$vaddr, $srsrc, $format, $soffset offen", 175 "$vaddr, $srsrc, $format, $soffset idxen", 177 "$vaddr, $srsrc, $format, $soffset idxen offen", 179 "$vaddr, $srsrc, $format, $soffset addr64", [all …]
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D | MIMGInstructions.td | 227 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 231 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 239 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask, 243 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe" 252 (ins SReg_256:$srsrc, DMask:$dmask, 256 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe" 320 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 324 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 332 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 336 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe" [all …]
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D | SIInstrFormats.td | 274 bits<7> srsrc; 286 let Inst{52-48} = srsrc{6-2};
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D | SILoadStoreOptimizer.cpp | 531 AddrOpName[NumAddresses++] = AMDGPU::OpName::srsrc; in setMI() 1250 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferLoadPair() 1315 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferLoadPair() 1394 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferStorePair() 1554 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferStorePair()
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D | SIRegisterInfo.cpp | 597 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore() 1035 TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(), in eliminateFrameIndex() 1065 TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(), in eliminateFrameIndex()
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D | SIInstructions.td | 547 (ins vgpr_class:$vdata, i32imm:$vaddr, SReg_128:$srsrc, 559 (ins i32imm:$vaddr, SReg_128:$srsrc, SReg_32:$soffset, 587 (ins vgpr_class:$vdata, i32imm:$vaddr, SReg_128:$srsrc, 599 (ins i32imm:$vaddr, SReg_128:$srsrc, SReg_32:$soffset,
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D | SIInstrInfo.cpp | 219 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)) in areLoadsFromSameBasePtr() 334 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); in getMemOperandWithOffset() 3656 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc); in verifyInstruction() 4660 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc); in legalizeOperands() 4676 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); in legalizeOperands() 6032 int RSrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in getInstSizeInBytes()
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D | GCNHazardRecognizer.cpp | 703 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc); in createsVALUHazard()
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D | SIFoldOperands.cpp | 620 if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() != in foldOperand()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
D | SIMCCodeEmitter.cpp | 297 int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in encodeInstruction() local 298 AMDGPU::OpName::srsrc); in encodeInstruction() 299 assert(vaddr0 >= 0 && srsrc > vaddr0); in encodeInstruction() 300 unsigned NumExtraAddrs = srsrc - vaddr0 - 1; in encodeInstruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
D | AMDGPUDisassembler.cpp | 377 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); in getInstruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
D | AMDGPUAsmParser.cpp | 2985 int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in validateMIMGAddrSize()
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