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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/
Dregengine.inc305 sopno ssub; /* start sop of subsubRE */
364 ssub = ss + 1;
367 if (slow(m, sp, rest, ssub, esub) != NULL) {
368 const char *dp = dissect(m, sp, rest, ssub, esub);
389 ssub = ss + 1;
394 sep = slow(m, ssp, rest, ssub, esub);
406 assert(slow(m, ssp, sep, ssub, esub) == rest);
408 const char *dp = dissect(m, ssp, sep, ssub, esub);
428 ssub = ss + 1;
432 if (slow(m, sp, rest, ssub, esub) == rest)
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/lib/Support/
Dregengine.inc305 sopno ssub; /* start sop of subsubRE */
364 ssub = ss + 1;
367 if (slow(m, sp, rest, ssub, esub) != NULL) {
368 const char *dp = dissect(m, sp, rest, ssub, esub);
389 ssub = ss + 1;
394 sep = slow(m, ssp, rest, ssub, esub);
406 assert(slow(m, ssp, sep, ssub, esub) == rest);
408 const char *dp = dissect(m, ssp, sep, ssub, esub);
428 ssub = ss + 1;
432 if (slow(m, sp, rest, ssub, esub) == rest)
[all …]
/third_party/ltp/tools/sparse/sparse-src/validation/optim/
Dbinops-same-args.c3 int ssub(int a) { return a - a; } in ssub() function
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc800 ssub, // 14
1129 { 0, 32 }, // ssub
5191 …, "dsub3", "hsub", "qhisub", "qsub", "qsub0", "qsub1", "qsub2", "qsub3", "ssub", "sub_32", "sube32…
5209 LaneBitmask(0x00000001), // ssub
5459 0x08010000, 0xffffffc0, 0xffffffff, 0x00000fff, // ssub
8940 …::hsub, 0, 0, AArch64::qsub0, AArch64::qsub1, AArch64::qsub2, 0, AArch64::ssub, AArch64::sub_32, A…
8950 …1_then_zsub, AArch64::zsub2_then_zsub, AArch64::zsub3_then_zsub, AArch64::ssub, 0, 0, 0, 0, 0, 0, …
8951 …dsub, AArch64::zsub3_then_dsub, AArch64::hsub, 0, 0, 0, 0, 0, 0, AArch64::ssub, 0, 0, 0, 0, 0, 0, …
9030 &LaneMaskComposeSequences[0], // to ssub
9161 0, // ssub
[all …]
DAArch64GenGlobalISel.inc43546 …R64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] }))
43586 …R64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] }))
43706 … }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] }))
43745 …i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] }))
/third_party/glib/gio/
Dgfileinfo.c2493 SubMatcher *msub, *ssub; in g_file_attribute_matcher_subtract() local
2510 ssub = &g_array_index (subtract->sub_matchers, SubMatcher, si); in g_file_attribute_matcher_subtract()
2517 if (sub_matcher_matches (ssub, msub)) in g_file_attribute_matcher_subtract()
2524 ssub = &g_array_index (subtract->sub_matchers, SubMatcher, si); in g_file_attribute_matcher_subtract()
2525 if (ssub->id <= msub->id) in g_file_attribute_matcher_subtract()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2098 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
2099 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
2101 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
2102 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
2258 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
2262 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
2839 defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, ssub, STRSroW, STRSroX>;
2840 defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, ssub, STRSroW, STRSroX>;
2961 defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, ssub, uimm12s4, STRSui>;
2962 defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, ssub, uimm12s4, STRSui>;
[all …]
DAArch64InstructionSelector.cpp410 SubReg = AArch64::ssub; in getSubRegForClass()
2797 return BuildFn(AArch64::ssub); in emitScalarToVector()
2886 ExtractSubReg = AArch64::ssub; in getLaneCopyOpcode()
3213 SubregIdx = AArch64::ssub; in getInsertVecEltOpInfo()
3229 SubregIdx = AArch64::ssub; in getInsertVecEltOpInfo()
3953 if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) { in selectInsertElt()
4021 if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) { in selectBuildVector()
DAArch64RegisterInfo.td26 def ssub : SubRegIndex<32>;
352 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
DAArch64InstrInfo.cpp2718 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub, in copyPhysReg()
2720 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub, in copyPhysReg()
3344 case AArch64::ssub: in foldMemoryOperandImpl()
3350 SpillSubreg = AArch64::ssub; in foldMemoryOperandImpl()
3390 case AArch64::ssub: in foldMemoryOperandImpl()
DAArch64InstrFormats.td7825 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
7837 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
8222 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
8224 ssub)>;
10081 ssub)),
10085 ssub)>;
10115 ssub)),
10119 ssub)>;
DSVEInstrFormats.td6514 …def : SVE_2_Op_Pat_Reduce_To_Neon<v4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S), ssub>;
6526 …def : SVE_2_Op_Pat_Reduce_To_Neon<v4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S), ssub>;
DAArch64ISelLowering.cpp5114 setVecVal(AArch64::ssub); in LowerFCOPYSIGN()
5148 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel); in LowerFCOPYSIGN()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc249 ssub_sat, // llvm.ssub.sat
250 ssub_with_overflow, // llvm.ssub.with.overflow
DIntrinsicImpl.inc277 "llvm.ssub.sat",
278 "llvm.ssub.with.overflow",
10410 4, // llvm.ssub.sat
10411 4, // llvm.ssub.with.overflow
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen136 ssub_with_overflow, // llvm.ssub.with.overflow
6160 "llvm.ssub.with.overflow",
14045 1, // llvm.ssub.with.overflow
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen144 ssub_with_overflow, // llvm.ssub.with.overflow
6202 "llvm.ssub.with.overflow",
14142 1, // llvm.ssub.with.overflow
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen144 ssub_with_overflow, // llvm.ssub.with.overflow
6202 "llvm.ssub.with.overflow",
14142 1, // llvm.ssub.with.overflow
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen144 ssub_with_overflow, // llvm.ssub.with.overflow
6202 "llvm.ssub.with.overflow",
14142 1, // llvm.ssub.with.overflow
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen144 ssub_with_overflow, // llvm.ssub.with.overflow
6202 "llvm.ssub.with.overflow",
14142 1, // llvm.ssub.with.overflow