Searched refs:stencil_only_unrestricted_pipeline (Results 1 – 2 of 2) sorted by relevance
355 state->clear[i].stencil_only_unrestricted_pipeline[j], &state->alloc); in radv_device_finish_meta_clear_state()700 ? &meta_state->clear[samples_log2].stencil_only_unrestricted_pipeline[index] in pick_depthstencil_pipeline()1385 &state->clear[i].stencil_only_unrestricted_pipeline[j], in radv_device_init_meta_clear_state()
427 VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES]; member