Home
last modified time | relevance | path

Searched refs:tess_offchip_offset (Results 1 – 7 of 7) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shader_llvm_tess.c457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
867 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
874 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
916 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1012 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1038 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
Dsi_shader.c431 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_init_shader_args()
451 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_init_shader_args()
519 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_init_shader_args()
606 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_init_shader_args()
611 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_init_shader_args()
Dgfx10_shader_ngg.c1208 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 4); in gfx10_emit_ngg_culling_epilogue()
/third_party/mesa3d/src/amd/common/
Dac_shader_args.h85 struct ac_arg tess_offchip_offset; member
/third_party/mesa3d/src/amd/vulkan/
Dradv_shader_args.c600 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
627 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
646 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
651 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
668 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
/third_party/mesa3d/src/amd/llvm/
Dac_nir_to_llvm.c4013 result = ac_get_arg(&ctx->ac, ctx->args->tess_offchip_offset); in visit_intrinsic()
/third_party/mesa3d/src/amd/compiler/
Daco_instruction_selection.cpp8844 get_arg(ctx, ctx->args->ac.tess_offchip_offset)); in visit_intrinsic()