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Searched refs:txr (Results 1 – 5 of 5) sorted by relevance

/third_party/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_state_init.c587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState()
588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState()
589 ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 ); in radeonInitState()
621 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0); in radeonInitState()
622 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1); in radeonInitState()
623 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2); in radeonInitState()
Dradeon_context.h326 struct radeon_state_atom txr[3]; /* for NPOT */ member
Dradeon_blit.c417 r100->hw.txr[0].dirty = GL_TRUE; in r100_blit()
Dradeon_texstate.c730 uint32_t *txr_cmd = &rmesa->hw.txr[unit].cmd[TXR_CMD_0]; in import_tex_obj_state()
733 RADEON_STATECHANGE( rmesa, txr[unit] ); in import_tex_obj_state()
Dradeon_ioctl.c78 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.txr[i]); in radeonSetUpAtomList()