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Searched refs:v16i16 (Results 1 – 25 of 27) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp388 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
389 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
390 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
391 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
414 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. in getArithmeticInstrCost()
415 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. in getArithmeticInstrCost()
418 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. in getArithmeticInstrCost()
419 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. in getArithmeticInstrCost()
451 { ISD::SHL, MVT::v16i16, 1 }, // psllw. in getArithmeticInstrCost()
452 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. in getArithmeticInstrCost()
[all …]
DX86InstrVecCompiler.td75 defm : subvector_subreg_lowering<VR128, v8i16, VR256, v16i16, sub_xmm>;
97 defm : subvector_subreg_lowering<VR256, v16i16, VR512, v32i16, sub_ymm>;
119 defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, v8i32, sub_xmm>;
128 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i16, v8i16, v8i32, sub_xmm>;
142 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, v16i32, sub_ymm>;
158 defm : subvec_zero_lowering<"DQAY", VR256, v32i16, v16i16, v16i32, sub_ymm>;
DX86CallingConv.td115 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
146 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
551 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
573 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
621 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
685 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
743 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
759 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td159 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
562 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
570 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
2301 def : Pat<(v16i16 (and VR256:$src1, VR256:$src2)),
2308 def : Pat<(v16i16 (or VR256:$src1, VR256:$src2)),
2315 def : Pat<(v16i16 (xor VR256:$src1, VR256:$src2)),
2322 def : Pat<(v16i16 (X86andnp VR256:$src1, VR256:$src2)),
2361 def : Pat<(v16i16 (and VR256:$src1, VR256:$src2)),
2370 def : Pat<(v16i16 (or VR256:$src1, VR256:$src2)),
2379 def : Pat<(v16i16 (xor VR256:$src1, VR256:$src2)),
[all …]
DX86ISelLowering.cpp1134 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) in X86TargetLowering()
1142 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) in X86TargetLowering()
1151 addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass in X86TargetLowering()
1208 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1221 setOperationAction(ISD::ROTL, MVT::v16i16, Custom); in X86TargetLowering()
1230 setOperationAction(ISD::SELECT, MVT::v16i16, Custom); in X86TargetLowering()
1234 for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1245 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1266 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1273 setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
[all …]
DX86InstrAVX512.td455 def : Pat<(v16i16 immAllZerosV), (AVX512_256_SET0)>;
938 (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
967 (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
1423 def : Pat<(v16i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))),
1431 def : Pat<(v16i16 (X86VBroadcast
1434 def : Pat<(v16i16 (X86VBroadcast
1441 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
1502 def : Pat<(v32i16 (X86SubVBroadcast (v16i16 VR256X:$src))),
1504 (v16i16 VR256X:$src), 1)>;
1566 def : Pat<(v16i16 (X86SubVBroadcast (loadv8i16 addr:$src))),
[all …]
DX86InstrFragmentsSIMD.td804 def loadv16i16 : PatFrag<(ops node:$ptr), (v16i16 (load node:$ptr))>;
859 (v16i16 (alignedload node:$ptr))>;
991 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
DX86RegisterInfo.td559 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
592 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
DX86InstrXOP.td398 def : Pat<(v16i16 (or (and VR256:$src3, VR256:$src1),
DX86ISelDAGToDAG.cpp4031 case MVT::v16i16: in getVPTESTMOpc()
4078 case MVT::v16i16: in getVPTESTMOpc()
4108 case MVT::v16i16: in getVPTESTMOpc()
4155 case MVT::v16i16: in getVPTESTMOpc()
DX86FastISel.cpp428 case MVT::v16i16: in X86FastEmitLoad()
601 case MVT::v16i16: in X86FastEmitStore()
DX86InstrCompiler.td613 def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
636 def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h87 v16i16 = 39, // 16 x i16 enumerator
361 SimpleTy == MVT::v16i16 || SimpleTy == MVT::v8i32 || in is256BitVector()
465 case v16i16: in getVectorElementType()
587 case v16i16: in getVectorNumElements()
778 case v16i16: in getSizeInBits()
952 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc1519 …{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPADDWYrr:{ *:[v16i16…
1530 …:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPADDWZ256rr:{ *:[v16i…
2063 …{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPSUBWYrr:{ *:[v16i16…
2074 …:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPSUBWZ256rr:{ *:[v16i…
2490 …{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMULLWYrr:{ *:[v16i1…
2501 …[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMULLWZ256rr:{ *:[v16i…
3857 …:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPANDYrr:{ *:[v16i16…
3868 …{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VANDPSYrr:{ *:[v16i16…
3879 …:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPANDQZ256rr:{ *:[v16i…
5431 …:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPORYrr:{ *:[v16i16]…
[all …]
DX86GenFastISel.inc94 if (RetVT.SimpleTy != MVT::v16i16)
183 case MVT::v16i16: return fastEmit_ISD_ABS_MVT_v16i16_r(RetVT, Op0, Op0IsKill);
288 case MVT::v16i16: return fastEmit_ISD_ANY_EXTEND_MVT_v16i1_MVT_v16i16_r(Op0, Op0IsKill);
683 if (RetVT.SimpleTy != MVT::v16i16)
763 case MVT::v16i16: return fastEmit_ISD_CTPOP_MVT_v16i16_r(RetVT, Op0, Op0IsKill);
1413 case MVT::v16i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i1_MVT_v16i16_r(Op0, Op0IsKill);
1469 case MVT::v16i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i8_MVT_v16i16_r(Op0, Op0IsKill);
1553 case MVT::v16i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i16_r(RetVT, Op0, Op0IsKill);
2600 case MVT::v16i16: return fastEmit_ISD_TRUNCATE_MVT_v16i32_MVT_v16i16_r(Op0, Op0IsKill);
2641 case MVT::v16i16: return fastEmit_ISD_TRUNCATE_MVT_v16i16_r(RetVT, Op0, Op0IsKill);
[all …]
DX86GenCallingConv.inc914 LocVT == MVT::v16i16 ||
1007 LocVT == MVT::v16i16 ||
1136 LocVT == MVT::v16i16 ||
1184 LocVT == MVT::v16i16 ||
1248 LocVT == MVT::v16i16 ||
1561 LocVT == MVT::v16i16 ||
1627 LocVT == MVT::v16i16 ||
1698 LocVT == MVT::v16i16 ||
1986 LocVT == MVT::v16i16 ||
2079 LocVT == MVT::v16i16 ||
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp262 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
263 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
289 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
290 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp320 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
321 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
609 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 }, in getCmpSelInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp184 case MVT::v16i16: return VectorType::get(Type::getInt16Ty(Context), 16); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td62 def v16i16 : ValueType<256, 39>; // 16 x i16 vector value
/third_party/openh264/codec/common/loongarch/
Dsatd_sad_lasx.c256 v16i16 mask= {1, 0, 3, 2, 5, 4, 7, 6, 1, 0, 3, 2, 5, 4, 7, 6}; in WelsSampleSatd4x4_lasx()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPatternsHVX.td355 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i16)),
DHexagonISelLoweringHVX.cpp198 for (MVT T: {MVT::v32i8, MVT::v32i16, MVT::v16i8, MVT::v16i16, MVT::v16i32}) in initializeHVXLowering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td252 def llvm_v16i16_ty : LLVMType<v16i16>; // 16 x i16
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp113 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Custom); in R600TargetLowering()

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