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Searched refs:v8i8 (Results 1 – 25 of 51) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
D	AArch64SchedFalkorDetails.td	643 (instregex "^ML(A\|S)(v8i8\|v4i16\|v2i32)(_indexed)?$")>; 658 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^ADD(v1i64\|v2i32\|v4i16\|v8i8)$")>; 660 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(AND\|ORR\|ORN\|BIC\|EOR)v8i8$")>; 662 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^NEG(v1i64\|v2i32\|v4i16\|v8i8)$")>; 663 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^SUB(v1i64\|v2i32\|v4i16\|v8i8)$")>; 665 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S\|U)(ADDLP\|HADD\|HSUB\|SHL)(v2i32\|v4i16\|v8i8)(_v.… 667 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S\|U)SHR(v2i32\|v4i16\|v8i8)_shift$")>; 669 …_2cyc], (instregex "^((S\|U)?(MAX\|MIN)P?\|ABS\|ADDP\|CM(EQ\|GE\|HS\|GT\|HI))(v1i64\|v2i32\|v4i16\|v8i8)$")>; 670 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ\|GE\|HS\|GT\|HI)(v1i64\|v2i32\|v4i16\|v8i8)$")>; 671 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ\|LE\|GE\|GT\|LT)(v1i64\|v2i32\|v4i16\|v8i8)rz$")>; [all …]
D	AArch64ISelDAGToDAG.cpp	`3182 if (VT == MVT::v8i8) { in Select() 3209 if (VT == MVT::v8i8) { in Select() 3236 if (VT == MVT::v8i8) { in Select() 3263 if (VT == MVT::v8i8) { in Select() 3290 if (VT == MVT::v8i8) { in Select() 3317 if (VT == MVT::v8i8) { in Select() 3344 if (VT == MVT::v8i8) { in Select() 3371 if (VT == MVT::v8i8) { in Select() 3398 if (VT == MVT::v8i8) { in Select() 3425 if (VT == MVT::v16i8 \|\| VT == MVT::v8i8) { in Select() [all …]`
D	AArch64TargetTransformInfo.cpp	304 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost() 312 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 313 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 316 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost() 317 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost() 348 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 }, in getCastInstrCost() 350 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 }, in getCastInstrCost() 943 {ISD::ADD, MVT::v8i8, 1}, in getArithmeticReductionCost() 962 { TTI::SK_Broadcast, MVT::v8i8, 1 }, in getShuffleCost() 974 { TTI::SK_Transpose, MVT::v8i8, 1 }, in getShuffleCost()
D	AArch64SchedKryoDetails.td	19 (instregex "(S\|U)R?SRA(d\|(v2i32\|v4i16\|v8i8)_shift)")>; 33 (instregex "(S\|U)ABA(v8i8\|v4i16\|v2i32)")>; 57 (instregex "(S\|U)(ABD\|RHADD)(v8i8\|v4i16\|v2i32)")>; 69 (instregex "(S\|U)ADALP(v8i8\|v4i16\|v2i32)_v.")>; 87 (instregex "((S\|U)ADDLP\|ABS)(v2i32\|v4i16\|v8i8)(_v.)?")>; 171 (instregex "((S\|U)H(ADD\|SUB)\|ADDP)(v8i8\|v4i16\|v2i32)")>; 201 (instregex "^(S\|U)QADD(v8i8\|v4i16\|v2i32)")>; 219 (instregex "(S\|U)QSHLU?(d\|s\|h\|b\|(v8i8\|v4i16\|v2i32)_shift)$")>; 231 (instregex "(S\|U)(QSHL\|RSHL\|QRSHL)(v1i8\|v1i16\|v1i32\|v1i64\|v8i8\|v4i16\|v2i32)$")>; 255 (instregex "((S\|U)QR?SHRN\|SQR?SHRUN)(v8i8\|v4i16\|v2i32)_shift?")>; [all …]
D	AArch64InstrInfo.td	2089 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>; 2136 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>; 2239 def : Pat <(v8i8 (scalar_to_vector (i32 2241 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), 2276 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2464 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2799 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>; 2891 def : Pat<(store (v8i8 FPR64:$Rt), 3028 def : Pat<(store (v8i8 FPR64:$Rt), 3154 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off), [all …]
D	AArch64CallingConvention.td	36 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8], 109 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 118 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], 135 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8], 151 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 226 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 242 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], 263 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 285 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 347 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
D	AArch64InstrFormats.td	5148 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64, 5150 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>; 5172 def : Pat<(v8i8 (OpNode V64:$LHS, V64:$RHS)), 5173 (!cast<Instruction>(inst#"v8i8") V64:$LHS, V64:$RHS)>; 5192 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64, 5194 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>; 5214 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b001, opc, V64, 5216 [(set (v8i8 V64:$dst), 5217 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>; 5243 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64, [all …]
D	AArch64SchedA57.td	345 // D form - v8i8, v4i16, v2i32 353 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8\|v4i16\|v2i32)$")>; 360 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8\|v4i16\|v2i32)v$")>; 369 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN\|MAX)V(v8i8\|v8i16)v$")>; 374 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL\|SQR?DMULH)(v8i8\|v4i16\|v2i32\|v1i8\|v1i16\|v1i32\|v… 379 def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8\|v4i16\|v2i32)(_indexed)?$")>; 391 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8\|v16i8)")>; 410 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8\|v1i16\|v1i32\|v1i64\|v8i8\|v4i16\|v2… 498 // D form - v8i8, v4i16, v2i32
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
D	HexagonCallingConv.td	`17 CCIfType<[i64,v2i32,v4i16,v8i8], 43 CCIfType<[i64,v2i32,v4i16,v8i8], 45 CCIfType<[i64,v2i32,v4i16,v8i8], 69 CCIfType<[i64,v2i32,v4i16,v8i8],`
D	HexagonPatterns.td	86 def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>; 442 // All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8. 445 defm: NopCast_pat<i64, v8i8, DoubleRegs>; 447 defm: NopCast_pat<v2i32, v8i8, DoubleRegs>; 448 defm: NopCast_pat<v4i16, v8i8, DoubleRegs>; 484 def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>; 497 def: Pat<(v8i8 (azext V8I1:$Pu)), 986 def: Pat<(v8i8 (HexagonVSPLAT I32:$Rs)), (S6_vsplatrbp I32:$Rs)>, 988 def: Pat<(v8i8 (HexagonVSPLAT I32:$Rs)), 1357 def: OpR_RR_pat<A2_vaddub, Add, v8i8, V8I8>; [all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
D	ARMInstrNEON.td	539 def SDTARMVTBL1 : SDTypeProfile<1, 2, [SDTCisVT<0, v8i8>, SDTCisVT<1, v8i8>, 540 SDTCisVT<2, v8i8>]>; 541 def SDTARMVTBL2 : SDTypeProfile<1, 3, [SDTCisVT<0, v8i8>, SDTCisVT<1, v8i8>, 542 SDTCisVT<2, v8i8>, SDTCisVT<3, v8i8>]>; 1064 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> { 1106 def : Pat<(insert_subvector (v16i8 undef), (v8i8 DPR:$src), (i32 0)), 1380 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8, 2125 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8, 2176 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8, 3319 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4, [all …]
D	ARMTargetTransformInfo.cpp	204 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost() 205 {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost() 229 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 230 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 231 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost() 232 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost() 240 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost() 365 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, in getCastInstrCost() 366 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, in getCastInstrCost() 586 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, in getShuffleCost() [all …]
D	ARMCallingConv.td	33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, 59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, 74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, 94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, 111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, 168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, 185 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, 211 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, 233 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
D	ARMScheduleA57.td	`985 (instregex "VABA(s\|u)(v8i8\|v4i16\|v2i32)")>; 1028 "VMUL(v8i8\|v4i16\|v2i32\|pd)", "VMULsl(v4i16\|v2i32)", 1050 (instregex "VMLA(sl)?(v8i8\|v4i16\|v2i32)", "VMLS(sl)?(v8i8\|v4i16\|v2i32)")>; 1127 "VSLI(v8i8\|v4i16\|v2i32\|v1i64)", "VSRI(v8i8\|v4i16\|v2i32\|v1i64)")>; 1135 "VSHL(s\|u)(v8i8\|v4i16\|v2i32\|v1i64)")>; 1144 "VQRSHL(s\|u)(v8i8\|v4i16\|v2i32\|v1i64)", "VQSHL(s\|u)(v8i8\|v4i16\|v2i32\|v1i64)", 1145 "VRSHL(s\|u)(v8i8\|v4i16\|v2i32\|v1i64)")>; 1220 "VMOV(v8i8\|v16i8\|v4i16\|v8i16\|v2i32\|v4i32\|v1i64\|v2i64\|v2f32\|v4f32)",`
D	ARMScheduleR52.td	764 def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABA(u\|s)(v8i8\|v4i… 768 def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VABD(u\|s)(v8i8\|v4i16\|v2i32)")>; 775 (instregex "(VADD\|VSUB)(v8i8\|v4i16\|v2i32\|v1i64)")>; 779 (instregex "(VADDHN\|VRADDHN\|VSUBHN\|VRSUBHN)(v8i8\|v4i16\|v2i32)")>; 809 def : InstRW<[R52WriteFPALU_F4, R52Read_F2, R52Read_F2], (instregex "(VHADD\|VHSUB)(u\|s)(v8i8\|v4i16\|… 819 def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VQABS(v8i8\|v4i16\|v2i32\|v1i64)")>; 822 (instregex "(VQADD\|VQSUB)(u\|s)(v8i8\|v4i16\|v2i32\|v1i64)")>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
D	ARMGenDAGISel.inc	1214 /* 2574/ OPC_SwitchType /2 cases /, 48, MVT::v8i8,// ->2625 1225 …2i32] } DPR:{ :[v2i32] }:$Vd, (bitconvert:{ :[v2i32] } (ARMvmovImm:{ :[v8i8] } (timm:{ :[i32] … 1233 …1i64] } DPR:{ :[v1i64] }:$Vd, (bitconvert:{ :[v1i64] } (ARMvmovImm:{ :[v8i8] } (timm:{ :[i32] … 1268 / 2692/ OPC_CheckType, MVT::v8i8, 1280 …i32] }:$Vm, (xor:{ :[v2i32] } (bitconvert:{ :[v2i32] } (ARMvmovImm:{ :[v8i8] } (timm:{ :[i32] … 1296 / 2746/ OPC_CheckType, MVT::v8i8, 1308 …2i32] } DPR:{ :[v2i32] }:$Vd, (bitconvert:{ :[v2i32] } (ARMvmovImm:{ :[v8i8] } (timm:{ :[i32] … 1319 / 2790/ OPC_CheckType, MVT::v8i8, 1332 …:[v2i32] } (xor:{ :[v2i32] } (bitconvert:{ :[v2i32] } (ARMvmovImm:{ :[v8i8] } (timm:{ :[i32] … 1349 /* 2846*/ OPC_CheckType, MVT::v8i8, [all …]
D	ARMGenGlobalISel.inc	2710 …v8i8] } (intrinsic_wo_chain:{ :[v8i8] } 1662:{ :[iPTR] }, DPR:{ :[v8i8] }:$Vn, DPR:{ :[v8i8] }… 2735 …v8i8] } (intrinsic_wo_chain:{ :[v8i8] } 1663:{ :[iPTR] }, DPR:{ :[v8i8] }:$Vn, DPR:{ :[v8i8] }… 2760 …v8i8] } DPR:{ :[v8i8] }:$src1, (intrinsic_wo_chain:{ :[v8i8] } 1662:{ :[iPTR] }, DPR:{ :[v8i8]… 2785 …v8i8] } DPR:{ :[v8i8] }:$src1, (intrinsic_wo_chain:{ :[v8i8] } 1663:{ :[iPTR] }, DPR:{ :[v8i8]… 2808 …v8i8] } (mul:{ :[v8i8] } DPR:{ :[v8i8] }:$Vn, DPR:{ :[v8i8] }:$Vm), DPR:{ :[v8i8] }:$src1) =>… 2831 …v8i8] } DPR:{ :[v8i8] }:$src1, (mul:{ :[v8i8] } DPR:{ :[v8i8] }:$Vn, DPR:{ :[v8i8] }:$Vm)) =>… 2848 …// (add:{ :[v8i8] } DPR:{ :[v8i8] }:$Vn, DPR:{ :[v8i8] }:$Vm) => (VADDv8i8:{ :[v8i8] } DPR:{… 2884 …v8i8] } 1662:{ :[iPTR] }, DPR:{ :[v8i8] }:$Vn, DPR:{ :[v8i8] }:$Vm)), QPR:{ :[v8i16] }:$src1) … 2914 …v8i8] } 1663:{ :[iPTR] }, DPR:{ :[v8i8] }:$Vn, DPR:{ :[v8i8] }:$Vm)), QPR:{ :[v8i16] }:$src1) … 2944 …v8i8] } 1662:{ :[iPTR] }, DPR:{ :[v8i8] }:$Vn, DPR:{ :[v8i8] }:$Vm))) => (VABALsv8i16:{ :[v8… [all …]
D	ARMGenCallingConv.inc	`67 LocVT == MVT::v8i8 \|\| 237 LocVT == MVT::v8i8 \|\| 356 LocVT == MVT::v8i8 \|\| 423 LocVT == MVT::v8i8 \|\| 517 LocVT == MVT::v8i8 \|\| 605 LocVT == MVT::v8i8 \|\| 708 LocVT == MVT::v8i8 \|\| 822 LocVT == MVT::v8i8 \|\| 879 LocVT == MVT::v8i8 \|\|`
D	ARMGenFastISel.inc	347 case MVT::v8i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill); 421 if (RetVT.SimpleTy != MVT::v8i8) 443 case MVT::v8i8: return fastEmit_ARMISD_VREV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 452 if (RetVT.SimpleTy != MVT::v8i8) 516 case MVT::v8i8: return fastEmit_ARMISD_VREV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 529 if (RetVT.SimpleTy != MVT::v8i8) 635 case MVT::v8i8: return fastEmit_ARMISD_VREV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 667 if (RetVT.SimpleTy != MVT::v8i8) 731 case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 772 case MVT::v8i8: return fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill); [all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
D	X86TargetTransformInfo.cpp	1352 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, in getCastInstrCost() 1353 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, in getCastInstrCost() 1361 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, in getCastInstrCost() 1372 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, in getCastInstrCost() 1373 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, in getCastInstrCost() 1404 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, in getCastInstrCost() 1417 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, in getCastInstrCost() 1418 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, in getCastInstrCost() 1431 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, in getCastInstrCost() 1448 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, in getCastInstrCost() [all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
D	MachineValueType.h	`75 v8i8 = 28, // 8 x i8 enumerator 342 return (SimpleTy == MVT::v64i1 \|\| SimpleTy == MVT::v8i8 \|\| in is64BitVector() 448 case v8i8: in getVectorElementType() 599 case v8i8: in getVectorNumElements() 738 case v8i8: in getSizeInBits() 939 if (NumElements == 8) return MVT::v8i8; in getVectorVT()`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
D	AArch64GenGlobalISel.inc	2552 …:[iPTR] }, V64:{ :[v8i8] }:$Rn), V64:{ :[v4i16] }:$Rd) => (SADALPv8i8_v4i16:{ :[v4i16] } V64… 2572 …:[iPTR] }, V64:{ :[v8i8] }:$Rn), V64:{ :[v4i16] }:$Rd) => (UADALPv8i8_v4i16:{ :[v4i16] } V64… 2638 …16] } 371:{ :[iPTR] }, V64:{ :[v8i8] }:$Rn)) => (SADALPv8i8_v4i16:{ :[v4i16] } V64:{ :[v4i16… 2658 …16] } 429:{ :[iPTR] }, V64:{ :[v8i8] }:$Rn)) => (UADALPv8i8_v4i16:{ :[v4i16] } V64:{ :[v4i16… 3204 …v8i8] } (intrinsic_wo_chain:{ :[v8i8] } 370:{ :[iPTR] }, V64:{ :[v8i8] }:$Rn, V64:{ :[v8i8] }:… 3227 …v8i8] } (intrinsic_wo_chain:{ :[v8i8] } 428:{ :[iPTR] }, V64:{ :[v8i8] }:$Rn, V64:{ :[v8i8] }:… 3250 …v8i8] } V64:{ :[v8i8] }:$Rd, (intrinsic_wo_chain:{ :[v8i8] } 370:{ :[iPTR] }, V64:{ :[v8i8] }:… 3273 …v8i8] } V64:{ :[v8i8] }:$Rd, (intrinsic_wo_chain:{ :[v8i8] } 428:{ :[iPTR] }, V64:{ :[v8i8] }:… 3288 …// (add:{ :[v8i8] } V64:{ :[v8i8] }:$Rn, V64:{ :[v8i8] }:$Rm) => (ADDv8i8:{ :[v8i8] } V64:{ … 3318 …v8i8] } 370:{ :[iPTR] }, V64:{ :[v8i8] }:$Rn, V64:{ :[v8i8] }:$Rm)), V128:{ :[v8i16] }:$Rd) =… [all …]
D	AArch64GenFastISel.inc	137 if (RetVT.SimpleTy != MVT::v8i8) 210 case MVT::v8i8: return fastEmit_AArch64ISD_CMEQz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 225 if (RetVT.SimpleTy != MVT::v8i8) 298 case MVT::v8i8: return fastEmit_AArch64ISD_CMGEz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 313 if (RetVT.SimpleTy != MVT::v8i8) 386 case MVT::v8i8: return fastEmit_AArch64ISD_CMGTz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 401 if (RetVT.SimpleTy != MVT::v8i8) 474 case MVT::v8i8: return fastEmit_AArch64ISD_CMLEz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 489 if (RetVT.SimpleTy != MVT::v8i8) 562 case MVT::v8i8: return fastEmit_AArch64ISD_CMLTz_MVT_v8i8_r(RetVT, Op0, Op0IsKill); [all …]
D	AArch64GenCallingConv.inc	`66 LocVT == MVT::v8i8) { 308 LocVT == MVT::v8i8 \|\| 364 LocVT == MVT::v8i8 \|\| 552 LocVT == MVT::v8i8 \|\| 625 LocVT == MVT::v8i8 \|\| 707 LocVT == MVT::v8i8 \|\| 789 LocVT == MVT::v8i8 \|\| 826 LocVT == MVT::v8i8 \|\| 1022 LocVT == MVT::v8i8) { 1121 LocVT == MVT::v8i8 \|\|`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
D	SystemZRegisterInfo.td	`126 [i64, f64, v8i8, v4i16, v2i32, v2f32], 64, 249 defm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64,`

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