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Searched refs:vram (Results 1 – 25 of 37) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h46 uint64_t vram, uint64_t gtt) in radeon_cs_memory_below_limit() argument
48 vram += (uint64_t)cs->used_vram_kb * 1024; in radeon_cs_memory_below_limit()
52 if (vram > screen->info.vram_size) in radeon_cs_memory_below_limit()
53 gtt += vram - screen->info.vram_size; in radeon_cs_memory_below_limit()
109 rctx->vram + rbo->vram_usage, in radeon_add_to_buffer_list_check_mem()
Dr600_hw_context.c41 ctx->b.vram, ctx->b.gtt)) { in r600_need_cs_space()
43 ctx->b.vram = 0; in r600_need_cs_space()
49 ctx->b.vram = 0; in r600_need_cs_space()
345 ctx->b.vram = 0; in r600_begin_new_cs()
Dr600_pipe_common.c231 uint64_t vram = (uint64_t)ctx->dma.cs.used_vram_kb * 1024; in r600_need_dma_space() local
235 vram += dst->vram_usage; in r600_need_dma_space()
239 vram += src->vram_usage; in r600_need_dma_space()
268 !radeon_cs_memory_below_limit(ctx->screen, &ctx->dma.cs, vram, gtt)) { in r600_need_dma_space()
Dr600_pipe_common.h520 uint64_t vram; member
844 rctx->vram += res->vram_usage; in r600_context_add_resource_size()
/third_party/mesa3d/src/mesa/drivers/dri/nouveau/
Dnv04_context.c88 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
89 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
95 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
103 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
Dnv20_context.c110 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
113 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
114 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
116 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
174 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
176 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
Dnv04_surface.c230 PUSH_DATA (push, fifo->vram); in nv04_surface_copy_swizzle()
238 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_copy_swizzle()
294 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_copy_m2mf()
295 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_copy_m2mf()
437 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_fill()
438 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_fill()
Dnv10_context.c215 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
219 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
220 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
251 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
252 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
Dnouveau_context.c145 .vram = 0xbeef0201, in nouveau_context_init()
/third_party/mesa3d/src/gallium/drivers/nouveau/nv30/
Dnv30_screen.c700 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */ in nv30_screen_create()
702 PUSH_DATA (push, fifo->vram); /* COLOR1 */ in nv30_screen_create()
704 PUSH_DATA (push, fifo->vram); /* COLOR0 */ in nv30_screen_create()
705 PUSH_DATA (push, fifo->vram); /* ZETA */ in nv30_screen_create()
706 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */ in nv30_screen_create()
732 PUSH_DATA (push, fifo->vram); in nv30_screen_create()
733 PUSH_DATA (push, fifo->vram); /* COLOR3 */ in nv30_screen_create()
Dnv30_transfer.c440 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
441 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
451 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
461 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
513 PUSH_DATA (push, (src->domain == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_rect_m2mf()
514 PUSH_DATA (push, (dst->domain == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_rect_m2mf()
704 PUSH_DATA (push, (s_dom == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_copy_data()
705 PUSH_DATA (push, (d_dom == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_copy_data()
/third_party/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv98_video.c91 struct nv04_fifo nv04_data = {.vram = 0xbeef0201, .gart = 0xbeef0202}; in nv98_create_decoder()
166 PUSH_DATA (push[0], nv04_data.vram); in nv98_create_decoder()
173 PUSH_DATA (push[1], nv04_data.vram); in nv98_create_decoder()
180 PUSH_DATA (push[2], nv04_data.vram); in nv98_create_decoder()
Dnv50_compute.c77 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
93 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
125 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
132 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
139 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
146 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
149 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
Dnv50_screen.c676 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
677 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
683 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
684 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
685 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
707 PUSH_DATA(push, fifo->vram); in nv50_screen_init_hwctx()
710 PUSH_DATA(push, fifo->vram); in nv50_screen_init_hwctx()
Dnv84_video.c274 struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 }; in nv84_create_decoder()
515 PUSH_DATA(bsp_push, nv04_data.vram); in nv84_create_decoder()
517 PUSH_DATA (bsp_push, nv04_data.vram); in nv84_create_decoder()
537 PUSH_DATA(vp_push, nv04_data.vram); in nv84_create_decoder()
540 PUSH_DATA (vp_push, nv04_data.vram); in nv84_create_decoder()
/third_party/mesa3d/src/gallium/drivers/iris/
Diris_bufmgr.c228 struct iris_memregion vram, sys; member
914 if (bufmgr->vram.size > 0) { in alloc_fresh_bo()
922 regions[nregions++] = bufmgr->vram.region; in alloc_fresh_bo()
966 if (bufmgr->vram.size == 0) { in alloc_fresh_bo()
993 bool local = bufmgr->vram.size > 0 && in iris_bo_alloc()
1012 (bufmgr->vram.size > 0 && !local) || in iris_bo_alloc()
1068 !bufmgr->has_llc && bufmgr->vram.size == 0) { in iris_bo_alloc()
1438 assert(bufmgr->vram.size == 0); in iris_bo_gem_mmap_legacy()
2152 bool local = bufmgr->vram.size > 0; in intel_aux_map_buffer_alloc()
2217 bufmgr->vram.region = mem->region; in iris_bufmgr_query_meminfo()
[all …]
/third_party/mesa3d/src/amd/common/
Dac_gpu_info.c69 struct drm_amdgpu_heap_info vram; member
499 info->vram_size = fix_vram_size(meminfo.vram.total_heap_size); in ac_query_gpu_info()
507 struct amdgpu_heap_info vram, vram_vis, gtt; in ac_query_gpu_info() local
509 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram); in ac_query_gpu_info()
529 info->vram_size = fix_vram_size(vram.heap_size); in ac_query_gpu_info()
/third_party/mesa3d/src/gallium/drivers/nouveau/
Dnouveau_video.c503 struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 }; in nouveau_create_decoder()
603 PUSH_DATA (push, nv04_data.vram); in nouveau_create_decoder()
619 PUSH_DATA (push, nv04_data.vram); in nouveau_create_decoder()
Dnouveau_screen.c194 struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 }; in nouveau_screen_init()
Dnouveau_vp3_video.c378 struct nv04_fifo nv04_data = {.vram = 0xbeef0201, .gart = 0xbeef0202}; in firmware_present()
/third_party/libdrm/nouveau/
Dnouveau.h245 uint32_t vram; member
Dabi16.c40 .fb_ctxdma_handle = nv04->vram, in abi16_chan_nv04()
/third_party/libdrm/include/drm/
Damdgpu_drm.h905 struct drm_amdgpu_heap_info vram; member
/third_party/mesa3d/src/intel/vulkan/
Danv_device.c386 region = &device->vram; in anv_gather_meminfo()
459 if (device->vram.size > 0) { in anv_physical_device_init_heaps()
465 .size = device->vram.size, in anv_physical_device_init_heaps()
874 memset(&device->vram, 0, sizeof(device->vram)); in anv_physical_device_try_create()
2591 mem_available = device->vram.available; in anv_get_memory_budget()
/third_party/mesa3d/include/drm-uapi/
Damdgpu_drm.h945 struct drm_amdgpu_heap_info vram; member

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