| /third_party/mesa3d/src/broadcom/qpu/ |
| D | qpu_instr.c | 32 enum v3d_qpu_waddr waddr) in v3d_qpu_magic_waddr_name() argument
35 if (devinfo->ver < 40 && waddr == V3D_QPU_WADDR_TMU) in v3d_qpu_magic_waddr_name()
82 return waddr_magic[waddr]; in v3d_qpu_magic_waddr_name()
530 v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr) in v3d_qpu_magic_waddr_is_sfu() argument
532 switch (waddr) { in v3d_qpu_magic_waddr_is_sfu()
547 enum v3d_qpu_waddr waddr) in v3d_qpu_magic_waddr_is_tmu() argument
550 return ((waddr >= V3D_QPU_WADDR_TMUD && in v3d_qpu_magic_waddr_is_tmu()
551 waddr <= V3D_QPU_WADDR_TMUAU) || in v3d_qpu_magic_waddr_is_tmu()
552 (waddr >= V3D_QPU_WADDR_TMUC && in v3d_qpu_magic_waddr_is_tmu()
553 waddr <= V3D_QPU_WADDR_TMUHSLOD)); in v3d_qpu_magic_waddr_is_tmu()
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| D | qpu_instr.h | 296 uint8_t waddr; member
306 uint8_t waddr; member
393 enum v3d_qpu_waddr waddr);
446 bool v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
448 enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
449 bool v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
450 bool v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
451 bool v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
452 bool v3d_qpu_magic_waddr_loads_unif(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
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| D | qpu_disasm.c | 86 v3d_qpu_disasm_waddr(struct disasm_state *disasm, uint32_t waddr, bool magic) in v3d_qpu_disasm_waddr() argument
89 append(disasm, "rf%d", waddr); in v3d_qpu_disasm_waddr()
93 const char *name = v3d_qpu_magic_waddr_name(disasm->devinfo, waddr); in v3d_qpu_disasm_waddr()
97 append(disasm, "waddr UNKNOWN %d", waddr); in v3d_qpu_disasm_waddr()
116 v3d_qpu_disasm_waddr(disasm, instr->alu.add.waddr, in v3d_qpu_disasm_add()
159 v3d_qpu_disasm_waddr(disasm, instr->alu.mul.waddr, in v3d_qpu_disasm_mul()
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| D | qpu_pack.c | 748 uint32_t waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A); in v3d_qpu_add_unpack() local
785 switch (waddr) { in v3d_qpu_add_unpack()
873 instr->alu.add.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A); in v3d_qpu_add_unpack()
963 instr->alu.mul.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_M); in v3d_qpu_mul_unpack()
993 uint32_t waddr = instr->alu.add.waddr; in v3d_qpu_add_pack() local
1019 waddr = 0; in v3d_qpu_add_pack()
1023 waddr = 1; in v3d_qpu_add_pack()
1027 waddr = 2; in v3d_qpu_add_pack()
1195 *packed_instr |= QPU_SET_FIELD(waddr, V3D_QPU_WADDR_A); in v3d_qpu_add_pack()
1302 *packed_instr |= QPU_SET_FIELD(instr->alu.mul.waddr, V3D_QPU_WADDR_M); in v3d_qpu_mul_pack()
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| /third_party/mesa3d/src/broadcom/compiler/ |
| D | qpu_validate.c | 91 bool (*predicate)(enum v3d_qpu_waddr waddr)) in qpu_magic_waddr_matches() argument
98 predicate(inst->alu.add.waddr)) in qpu_magic_waddr_matches()
103 predicate(inst->alu.mul.waddr)) in qpu_magic_waddr_matches()
157 inst->alu.add.waddr)) { in qpu_validate_inst()
160 if (v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) in qpu_validate_inst()
162 if (v3d_qpu_magic_waddr_is_vpm(inst->alu.add.waddr)) in qpu_validate_inst()
164 if (v3d_qpu_magic_waddr_is_tlb(inst->alu.add.waddr)) in qpu_validate_inst()
166 if (v3d_qpu_magic_waddr_is_tsy(inst->alu.add.waddr)) in qpu_validate_inst()
174 inst->alu.mul.waddr)) { in qpu_validate_inst()
177 if (v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) in qpu_validate_inst()
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| D | vir_to_qpu.c | 39 qpu_magic(enum v3d_qpu_waddr waddr) in qpu_magic() argument
43 .index = waddr, in qpu_magic()
56 .waddr = V3D_QPU_WADDR_NOP, in v3d_qpu_nop()
61 .waddr = V3D_QPU_WADDR_NOP, in v3d_qpu_nop()
145 enum v3d_qpu_waddr waddr = qinst->qpu.alu.mul.waddr; in is_no_op_mov() local
147 if (waddr < V3D_QPU_WADDR_R0 || waddr > V3D_QPU_WADDR_R4) in is_no_op_mov()
151 V3D_QPU_MUX_R0 + (waddr - V3D_QPU_WADDR_R0)) { in is_no_op_mov()
167 if (raddr != waddr) in is_no_op_mov()
310 qinst->qpu.alu.add.waddr = dst.index; in v3d_generate_code_block()
322 qinst->qpu.alu.mul.waddr = dst.index; in v3d_generate_code_block()
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| D | qpu_schedule.c | 140 (inst->alu.add.waddr == V3D_QPU_WADDR_TLB || in qpu_inst_is_tlb()
141 inst->alu.add.waddr == V3D_QPU_WADDR_TLBU)) in qpu_inst_is_tlb()
145 (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB || in qpu_inst_is_tlb()
146 inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU)) in qpu_inst_is_tlb()
173 tmu_write_is_sequence_terminator(uint32_t waddr) in tmu_write_is_sequence_terminator() argument
175 switch (waddr) { in tmu_write_is_sequence_terminator()
189 can_reorder_tmu_write(const struct v3d_device_info *devinfo, uint32_t waddr) in can_reorder_tmu_write() argument
194 if (tmu_write_is_sequence_terminator(waddr)) in can_reorder_tmu_write()
197 if (waddr == V3D_QPU_WADDR_TMUD) in can_reorder_tmu_write()
205 uint32_t waddr, bool magic) in process_waddr_deps() argument
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| D | v3d40_tex.c | 34 vir_TMU_WRITE(struct v3d_compile *c, enum v3d_qpu_waddr waddr, struct qreg val) in vir_TMU_WRITE() argument
39 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, waddr), val); in vir_TMU_WRITE()
44 enum v3d_qpu_waddr waddr, in vir_TMU_WRITE_or_count() argument
51 vir_TMU_WRITE(c, waddr, val); in vir_TMU_WRITE_or_count()
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| /third_party/mesa3d/src/gallium/drivers/vc4/kernel/ |
| D | vc4_validate_shaders.c | 98 waddr_to_live_reg_index(uint32_t waddr, bool is_b) in waddr_to_live_reg_index() argument
100 if (waddr < 32) { in waddr_to_live_reg_index()
102 return 32 + waddr; in waddr_to_live_reg_index()
104 return waddr; in waddr_to_live_reg_index()
105 } else if (waddr <= QPU_W_ACC3) { in waddr_to_live_reg_index()
106 return 64 + waddr - QPU_W_ACC0; in waddr_to_live_reg_index()
137 is_tmu_submit(uint32_t waddr) in is_tmu_submit() argument
139 return (waddr == QPU_W_TMU0_S || in is_tmu_submit()
140 waddr == QPU_W_TMU1_S); in is_tmu_submit()
144 is_tmu_write(uint32_t waddr) in is_tmu_write() argument
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qpu_schedule.c | 186 is_tmu_write(uint32_t waddr) in is_tmu_write() argument
188 switch (waddr) { in is_tmu_write()
227 uint32_t waddr, bool is_add) in process_waddr_deps() argument
232 if (waddr < 32) { in process_waddr_deps()
234 add_write_dep(state, &state->last_ra[waddr], n); in process_waddr_deps()
236 add_write_dep(state, &state->last_rb[waddr], n); in process_waddr_deps()
238 } else if (is_tmu_write(waddr)) { in process_waddr_deps()
241 } else if (qpu_waddr_is_tlb(waddr) || in process_waddr_deps()
242 waddr == QPU_W_MS_FLAGS) { in process_waddr_deps()
245 switch (waddr) { in process_waddr_deps()
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| D | vc4_qpu_disasm.c | 299 uint32_t waddr = (is_mul ? in print_alu_dst() local
305 if (waddr <= 31) in print_alu_dst()
306 fprintf(stderr, "r%s%d", file, waddr); in print_alu_dst()
307 else if (get_special_write_desc(waddr, is_a)) in print_alu_dst()
308 fprintf(stderr, "%s", get_special_write_desc(waddr, is_a)); in print_alu_dst()
310 fprintf(stderr, "%s%d?", file, waddr); in print_alu_dst()
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| D | vc4_qpu.c | 319 qpu_waddr_ignores_ws(uint32_t waddr) in qpu_waddr_ignores_ws() argument
321 switch(waddr) { in qpu_waddr_ignores_ws()
657 qpu_waddr_is_tlb(uint32_t waddr) in qpu_waddr_is_tlb() argument
659 switch (waddr) { in qpu_waddr_is_tlb()
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| D | vc4_qpu.h | 155 bool qpu_waddr_is_tlb(uint32_t waddr) ATTRIBUTE_CONST;
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