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Searched refs:enc_pic (Results 1 – 11 of 11) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeon/
Dradeon_vce_52.c40 enc->enc_pic.rc.rc_method = pic->rate_ctrl[0].rate_ctrl_method; in get_rate_control_param()
41 enc->enc_pic.rc.target_bitrate = pic->rate_ctrl[0].target_bitrate; in get_rate_control_param()
42 enc->enc_pic.rc.peak_bitrate = pic->rate_ctrl[0].peak_bitrate; in get_rate_control_param()
43 enc->enc_pic.rc.quant_i_frames = pic->quant_i_frames; in get_rate_control_param()
44 enc->enc_pic.rc.quant_p_frames = pic->quant_p_frames; in get_rate_control_param()
45 enc->enc_pic.rc.quant_b_frames = pic->quant_b_frames; in get_rate_control_param()
46 enc->enc_pic.rc.gop_size = pic->gop_size; in get_rate_control_param()
47 enc->enc_pic.rc.frame_rate_num = pic->rate_ctrl[0].frame_rate_num; in get_rate_control_param()
48 enc->enc_pic.rc.frame_rate_den = pic->rate_ctrl[0].frame_rate_den; in get_rate_control_param()
49 enc->enc_pic.rc.max_qp = 51; in get_rate_control_param()
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Dradeon_vcn_enc_1_2.c69 RADEON_ENC_CS(enc->enc_pic.session_info.interface_version); in radeon_enc_session_info()
77 enc->enc_pic.task_info.task_id++; in radeon_enc_task_info()
80 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1; in radeon_enc_task_info()
82 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0; in radeon_enc_task_info()
86 RADEON_ENC_CS(enc->enc_pic.task_info.task_id); in radeon_enc_task_info()
87 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks); in radeon_enc_task_info()
93 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264; in radeon_enc_session_init()
94 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16); in radeon_enc_session_init()
95 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); in radeon_enc_session_init()
96 enc->enc_pic.session_init.padding_width = in radeon_enc_session_init()
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Dradeon_uvd_enc_1_1.c206 enc->enc_pic.task_info.task_id++; in radeon_uvd_enc_task_info()
209 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1; in radeon_uvd_enc_task_info()
211 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0; in radeon_uvd_enc_task_info()
215 RADEON_ENC_CS(enc->enc_pic.task_info.task_id); in radeon_uvd_enc_task_info()
216 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks); in radeon_uvd_enc_task_info()
222 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64); in radeon_uvd_enc_session_init_hevc()
223 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); in radeon_uvd_enc_session_init_hevc()
224 enc->enc_pic.session_init.padding_width = in radeon_uvd_enc_session_init_hevc()
225 enc->enc_pic.session_init.aligned_picture_width - enc->base.width; in radeon_uvd_enc_session_init_hevc()
226 enc->enc_pic.session_init.padding_height = in radeon_uvd_enc_session_init_hevc()
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Dradeon_vcn_enc_3_0.c43 enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0; in radeon_enc_spec_misc()
44 enc->enc_pic.spec_misc.cabac_enable = 0; in radeon_enc_spec_misc()
45 enc->enc_pic.spec_misc.cabac_init_idc = 0; in radeon_enc_spec_misc()
46 enc->enc_pic.spec_misc.half_pel_enabled = 1; in radeon_enc_spec_misc()
47 enc->enc_pic.spec_misc.quarter_pel_enabled = 1; in radeon_enc_spec_misc()
48 enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile); in radeon_enc_spec_misc()
49 enc->enc_pic.spec_misc.level_idc = enc->base.level; in radeon_enc_spec_misc()
50 enc->enc_pic.spec_misc.b_picture_enabled = 0; in radeon_enc_spec_misc()
51 enc->enc_pic.spec_misc.weighted_bipred_idc = 0; in radeon_enc_spec_misc()
54 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag); in radeon_enc_spec_misc()
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Dradeon_vcn_enc_2_0.c96 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6); in radeon_enc_slice_header_hevc()
109 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23)) in radeon_enc_slice_header_hevc()
126 switch (enc->enc_pic.picture_type) { in radeon_enc_slice_header_hevc()
142 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) { in radeon_enc_slice_header_hevc()
143 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc); in radeon_enc_slice_header_hevc()
144 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) in radeon_enc_slice_header_hevc()
154 if (enc->enc_pic.sample_adaptive_offset_enabled_flag) { in radeon_enc_slice_header_hevc()
165 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) || in radeon_enc_slice_header_hevc()
166 (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) { in radeon_enc_slice_header_hevc()
168 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1); in radeon_enc_slice_header_hevc()
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Dradeon_vcn_enc.c45 enc->enc_pic.picture_type = pic->picture_type; in radeon_vcn_enc_get_param()
46 enc->enc_pic.frame_num = pic->frame_num; in radeon_vcn_enc_get_param()
47 enc->enc_pic.pic_order_cnt = pic->pic_order_cnt; in radeon_vcn_enc_get_param()
48 enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type; in radeon_vcn_enc_get_param()
49 enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0; in radeon_vcn_enc_get_param()
50 enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1; in radeon_vcn_enc_get_param()
51 enc->enc_pic.not_referenced = pic->not_referenced; in radeon_vcn_enc_get_param()
52 enc->enc_pic.is_idr = (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR); in radeon_vcn_enc_get_param()
54 enc->enc_pic.crop_left = pic->pic_ctrl.enc_frame_crop_left_offset; in radeon_vcn_enc_get_param()
55 enc->enc_pic.crop_right = pic->pic_ctrl.enc_frame_crop_right_offset; in radeon_vcn_enc_get_param()
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Dradeon_uvd_enc.c56 enc->enc_pic.picture_type = pic->picture_type; in radeon_uvd_enc_get_param()
57 enc->enc_pic.frame_num = pic->frame_num; in radeon_uvd_enc_get_param()
58 enc->enc_pic.pic_order_cnt = pic->pic_order_cnt; in radeon_uvd_enc_get_param()
59 enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type; in radeon_uvd_enc_get_param()
60 enc->enc_pic.not_referenced = pic->not_referenced; in radeon_uvd_enc_get_param()
61 enc->enc_pic.is_iframe = (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) || in radeon_uvd_enc_get_param()
65 enc->enc_pic.crop_left = pic->seq.conf_win_left_offset; in radeon_uvd_enc_get_param()
66 enc->enc_pic.crop_right = pic->seq.conf_win_right_offset; in radeon_uvd_enc_get_param()
67 enc->enc_pic.crop_top = pic->seq.conf_win_top_offset; in radeon_uvd_enc_get_param()
68 enc->enc_pic.crop_bottom = pic->seq.conf_win_bottom_offset; in radeon_uvd_enc_get_param()
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Dradeon_uvd_enc.h414 struct radeon_uvd_enc_pic enc_pic; member
Dradeon_vce.h410 struct rvce_h264_enc_pic enc_pic; member
Dradeon_vcn_enc.h539 struct radeon_enc_pic enc_pic; member
/third_party/mesa3d/src/gallium/drivers/r600/
Dradeon_vce.h408 struct rvce_h264_enc_pic enc_pic; member