Lines Matching full:acc
28 GateAccessor acc(const_cast<Circuit*>(circuit)); in CalculateDominatorTree() local
35 auto startGate = acc.GetStateRoot(); in CalculateDominatorTree()
36 acc.SetMark(startGate, MarkCode::VISITED); in CalculateDominatorTree()
43 if (acc.GetOpCode(curGate) != OpCode::LOOP_BACK) { in CalculateDominatorTree()
44 auto uses = acc.Uses(curGate); in CalculateDominatorTree()
46 if (useIt.GetIndex() < acc.GetStateCount(*useIt) && in CalculateDominatorTree()
47 acc.IsState(*useIt) && acc.GetMark(*useIt) == MarkCode::NO_MARK) { in CalculateDominatorTree()
48 acc.SetMark(*useIt, MarkCode::VISITED); in CalculateDominatorTree()
86 acc.GetInStates(bbGatesList[idx], preGates); in CalculateDominatorTree()
127 GateAccessor acc(const_cast<Circuit*>(circuit)); in Run() local
209 acc.GetOuts(acc.GetArgRoot(), argList); in Run()
211 return acc.TryGetValue(lhs) > acc.TryGetValue(rhs); in Run()
217 auto uses = acc.Uses(bbGate); in Run()
220 if (acc.GetMetaData(succGate)->IsFixed()) { in Run()
221 result[bbGatesAddrToIdx.at(acc.GetIn(succGate, 0))].push_back(succGate); in Run()
237 GateAccessor acc(const_cast<Circuit*>(circuit)); in CalculateSchedulingUpperBound() local
252 } else if (acc.GetMetaData(gate)->IsProlog() || acc.GetMetaData(gate)->IsRoot()) { in CalculateSchedulingUpperBound()
255 } else if (acc.GetMetaData(gate)->IsFixed()) { in CalculateSchedulingUpperBound()
256 returnValue = bbGatesAddrToIdx.at(acc.GetIn(gate, 0)); in CalculateSchedulingUpperBound()
258 } else if (acc.GetMetaData(gate)->IsState()) { in CalculateSchedulingUpperBound()
277 acc.GetIns(schedulableGate, rootPredGates); in CalculateSchedulingUpperBound()
316 acc.GetIns(predGate, newPredGates); in CalculateSchedulingUpperBound()
343 GateAccessor acc(const_cast<Circuit*>(circuit)); in CalculateSchedulingLowerBound() local
348 auto uses = acc.Uses(item.first); in CalculateSchedulingLowerBound()
351 if (acc.GetMetaData(succGate)->IsFixed()) { in CalculateSchedulingLowerBound()
366 acc.GetIns(gate, rootPrevGates); in CalculateSchedulingLowerBound()
376 if (!acc.GetMetaData(prevGate)->IsSchedulable()) { in CalculateSchedulingLowerBound()
385 acc.GetIns(prevGate, newPrevGates); in CalculateSchedulingLowerBound()
402 acc.GetIns(gate, rootPrevGates); in CalculateSchedulingLowerBound()
413 if (!acc.GetMetaData(prevGate)->IsSchedulable()) { in CalculateSchedulingLowerBound()
419 if (acc.GetMetaData(curGate)->IsState()) { // cur_opcode would not be STATE_ENTRY in CalculateSchedulingLowerBound()
421 } else if (acc.GetMetaData(curGate)->IsFixed()) { in CalculateSchedulingLowerBound()
423 curLowerBound = bbGatesAddrToIdx.at(acc.GetIn(acc.GetIn(curGate, 0), idx - 1)); in CalculateSchedulingLowerBound()
440 acc.GetIns(prevGate, newPrevGates); in CalculateSchedulingLowerBound()
449 GateAccessor acc(const_cast<Circuit*>(circuit)); in Print() local
456 auto opcode = acc.GetOpCode((*cfg)[bbIdx].front()); in Print()
462 auto ins = acc.Ins(head); in Print()
465 if (acc.GetMetaData(predState)->IsState() || in Print()
466 acc.GetOpCode(predState) == OpCode::STATE_ENTRY) { in Print()
474 auto uses = acc.Uses(h); in Print()
477 if (acc.GetMetaData(succState)->IsState() || in Print()
478 acc.GetOpCode(succState) == OpCode::STATE_ENTRY) { in Print()
485 acc.Print((*cfg)[bbIdx][instIdx - 1]); in Print()