3  * TLB Management (flush/create/diagnostics) for ARC700
33  *  -In TLB Flush operations (Metal Fix MMU) there is a explicit command to
34  *    flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
39  *  -Reduced the duration of IRQ lockouts in TLB Flush routines
40  *  -Multiple copies of TLB erase code separated into a "single" function
41  *  -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
46  *              flush is more than the size of TLB itself.
62  * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
67  * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
68  * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
70  * J-TLB entries are created (even though 3rd will knock out one of the prev
71  * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
73  * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
78  * - Existing TLB commands work as before
79  * - New command (TLBWriteNI) for TLB write without clearing uTLBs
83  * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
87  * TLB.
92  * When the OS page table is updated, TLB entries that may be associated with a
93  * removed page are removed (flushed) from the TLB using TLBWrite. In this
97  * J-TLB entry got evicted/replaced.
107  * Utility Routine to erase a J-TLB entry
128 	 * fail when a prior probe for J-TLB (both totally unrelated) would  in utlb_invalidate()
166 	/* Locate the TLB entry for this vaddr + ASID */  in tlb_entry_erase()
198 	/* setup the other half of TLB entry (pfn, rwx..) */  in tlb_entry_insert()
252 		/* write this entry to the TLB */  in local_flush_tlb_all()
301  * Flush a Range of TLB entries for userland.
314 	/* If range @start to @end is more than 32 TLB entries deep,  in local_flush_tlb_range()
345 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
347  * Interestingly, shared TLB entries can also be flushed using just
355 	/* exactly same as above, except for TLB entry not taking ASID */  in local_flush_tlb_kernel_range()
374  * Delete TLB entry in MMU for a given page (??? address)
375  * NOTE One TLB entry contains translation for single PAGE
384 	 * checking the ASID and using it flush the TLB entry  in local_flush_tlb_page()
492  * Routine to create a TLB entry
503 	 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)  in create_tlb()
508 	 * -Fix the TLB paranoid debug code to not trigger false negatives.  in create_tlb()
510 	 *  TLB Refill handler which always deals with "current"  in create_tlb()
514 	 *     Here VM wants to pre-install a TLB entry for user stack while  in create_tlb()
517 	 *     move_page_tables() tries to undo that TLB entry.  in create_tlb()
518 	 *     Thus not creating TLB entry is not any worse.  in create_tlb()
521 	 *     breakpoint in debugged task. Not creating a TLB now is not  in create_tlb()
538 	/* Create HW TLB(PD0,PD1) from PTE  */  in create_tlb()
568  *  -pre-install the corresponding TLB entry into MMU
618  * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
619  * new bit "SZ" in TLB page descriptor to distinguish between them.
819 	 * revisions were not backwards compatible (MMUv3 TLB layout changed  in arc_mmu_init()
860  * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
876 /* Handling of Duplicate PD (TLB entry) in MMU.
898 	/* loop thru all sets of TLB */  in do_tlb_overlap_fault()
931 					pr_info("Dup TLB PD0 %08x @ set %d ways %d,%d\n",  in do_tlb_overlap_fault()
951  *  -Called from Low Level TLB Handlers if things don;t look good
957  * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
975 	 * At the time of a TLB miss/installation  in tlb_paranoid_check()