Lines Matching full:c0
32 mcr p14, 0, \ch, c0, c5, 0
38 mcr p14, 0, \ch, c8, c0, 0
44 mcr p14, 0, \ch, c1, c0, 0
139 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
143 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
484 mrc p15, 0, r1, c0, c1, 1 @ read ID_PFR1 register
756 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
795 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
796 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
797 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
800 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
801 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
807 mrc p15, 0, r0, c1, c0, 0 @ read control reg
812 mcr p15, 0, r0, c1, c0, 0 @ write control reg
824 mcr p15, 0, r0, c2, c0, 0 @ cache on
825 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
828 mcr p15, 0, r0, c5, c0, 0 @ access permission
831 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
836 mrc p15, 0, r0, c1, c0, 0 @ read control reg
841 mcr p15, 0, r0, c1, c0, 0 @ write control reg
844 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
901 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
904 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
910 mcr p15, 7, r0, c15, c0, 0
921 mrc p15, 0, r0, c1, c0, 0 @ read control reg
935 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
944 mrc p15, 0, r0, c1, c0, 0 @ read control reg
953 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
958 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
959 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
960 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
963 mcr p15, 0, r0, c1, c0, 0 @ load control register
964 mrc p15, 0, r0, c1, c0, 0 @ and read it back
977 mrc p15, 0, r0, c1, c0, 0 @ read control reg
990 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
991 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
994 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
995 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
1017 mrc p15, 0, r9, c0, c0 @ get processor ID
1224 mrc p15, 0, r0, c1, c0
1226 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1234 mrc p15, 0, r0, c1, c0
1236 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1238 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1243 mrc p15, 0, r0, c1, c0
1245 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1253 mrc p15, 0, r0, c1, c0
1259 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1327 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1365 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1399 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1546 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1548 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1576 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
1589 mcr p15, 4, r1, c1, c0, 0
1591 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1608 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR