Lines Matching +full:co +full:- +full:processor
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Processor Abstraction Layer definitions.
8 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
9 * chapter 11 IA-64 Processor Abstraction Layer
11 * Copyright (C) 1998-2001 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
21 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
30 * Note that some of these calls use a static-register only calling
42 #define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
43 #define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
47 #define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
49 #define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
50 #define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
51 #define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
54 #define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
57 #define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
58 #define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
65 #define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
66 #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
69 #define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
72 #define PAL_SHUTDOWN 40 /* enter processor shutdown state */
73 #define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
74 #define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping …
75 #define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */
78 #define PAL_VP_INFO 50 /* Information about virtual processor features */
82 #define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
83 #define PAL_TEST_PROC 258 /* perform late processor self-test */
87 #define PAL_GET_PSTATE 262 /* get the current P-state */
88 #define PAL_SET_PSTATE 263 /* set the P-state */
89 #define PAL_BRAND_INFO 274 /* Processor branding information */
96 #define PAL_MC_ERROR_INJECT 276 /* Injects processor error or returns injection capabilities */
112 #define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
113 #define PAL_STATUS_EINVAL (-2) /* Invalid argument */
114 #define PAL_STATUS_ERROR (-3) /* Error */
115 #define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
120 #define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */
122 /* Processor cache level in the hierarchy */
129 /* Processor cache type at a particular level in the hierarchy */
140 /* Processor cache line size in bytes */
143 /* Processor cache line state */
157 at : 2, /* 2-1 Cache mem attr*/
158 reserved : 5, /* 7-3 Reserved */
159 associativity : 8, /* 16-8 Associativity*/
160 line_size : 8, /* 23-17 Line size */
161 stride : 8, /* 31-24 Stride */
162 store_latency : 8, /*39-32 Store latency*/
163 load_latency : 8, /* 47-40 Load latency*/
164 store_hints : 8, /* 55-48 Store hints*/
165 load_hints : 8; /* 63-56 Load hints */
175 u32 alias_boundary : 8, /* 39-32 aliased addr
179 tag_ls_bit : 8, /* 47-40 LSb of addr*/
180 tag_ms_bit : 8, /* 55-48 MSb of addr*/
181 reserved : 8; /* 63-56 Reserved */
223 #define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
224 #define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
226 /* Processor cache protection information */
234 tagprot_lsb : 6, /* Least -do- */
256 /* Processor cache part encodings */
274 /* Processor cache protection method encodings */
281 /* Processor cache line identification in the hierarchy */
285 u64 cache_type : 8, /* 7-0 cache type */
286 level : 8, /* 15-8 level of the
290 way : 8, /* 23-16 way in the set
292 part : 8, /* 31-24 part of the
295 reserved : 32; /* 63-32 is reserved*/
298 u64 cache_type : 8, /* 7-0 cache type */
299 level : 8, /* 15-8 level of the
303 way : 8, /* 23-16 way in the set
305 part : 8, /* 31-24 part of the
308 mesi : 8, /* 39-32 cache line
311 start : 8, /* 47-40 lsb of data to
314 length : 8, /* 55-48 #bits to
317 trigger : 8; /* 63-56 Trigger error
339 /* Processor cache line part encodings */
351 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
369 #define PAL_MC_INFO_PROCESSOR 0 /* Processor */
384 rz : 1, /* PAL_CHECK processor
406 co : 1, /* Continuable */ member
413 hd : 1, /* Non-essential hw
417 * processor to run in
434 pm : 1, /* Precise min-state save area */
436 dy : 1, /* Processor dynamic
473 * by the processor
578 * during cache-cache
706 #define pmci_proc_continuable pme_processor.co
755 u64 pmsa_gr[15]; /* GR1 - GR15 */
756 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
757 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
880 /* Provide information about configurable processor bus features */
889 features_avail->pal_bus_features_val = iprv.v0; in ia64_pal_bus_get_features()
891 features_status->pal_bus_features_val = iprv.v1; in ia64_pal_bus_get_features()
893 features_control->pal_bus_features_val = iprv.v2; in ia64_pal_bus_get_features()
897 /* Enables/disables specific processor bus features */
915 conf->pcci_status = iprv.status; in ia64_pal_cache_config_info()
916 conf->pcci_info_1.pcci1_data = iprv.v0; in ia64_pal_cache_config_info()
917 conf->pcci_info_2.pcci2_data = iprv.v1; in ia64_pal_cache_config_info()
918 conf->pcci_reserved = iprv.v2; in ia64_pal_cache_config_info()
933 prot->pcpi_status = iprv.status; in ia64_pal_cache_prot_info()
934 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff; in ia64_pal_cache_prot_info()
935 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32; in ia64_pal_cache_prot_info()
936 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff; in ia64_pal_cache_prot_info()
937 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32; in ia64_pal_cache_prot_info()
938 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff; in ia64_pal_cache_prot_info()
939 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32; in ia64_pal_cache_prot_info()
945 * Flush the processor instruction or data caches. *PROGRESS must be
960 /* Initialize the processor controlled caches */
970 * processor controlled cache to known values without the availability
982 /* Read the data and tag of a processor controlled cache line for diags */
992 /* Return summary information about the hierarchy of caches controlled by the processor */
1005 /* Write the data and tag of a processor-controlled cache line for diags */
1032 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset) in ia64_pal_copy_pal() argument
1035 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor); in ia64_pal_copy_pal()
1056 /* Switch from IA64-system environment to IA-32 system environment */
1066 /* Get unique geographical address of this processor on its bus */
1077 /* Get base frequency of the platform if generated by the processor */
1088 * Get the ratios for processor frequency, bus frequency and interval timer to
1107 * Get the current hardware resource sharing policy of the processor
1124 /* Make the processor enter HALT or one of the implementation dependent low
1143 co : 1, member
1148 /* Return information about processor's optional power management capabilities. */
1157 /* Get the current P-state information */
1167 /* Set the P-state */
1176 /* Processor branding information*/
1185 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1196 /* Clear all the processor error logging registers and reset the indicator that allows
1210 /* Ensure that all outstanding transactions in a processor are completed or that any
1221 /* Return the machine check dynamic processor state */
1232 /* Return processor machine check information */
1245 /* Injects the requested processor error or returns info on
1246 * supported injection capabilities for current processor implementation
1314 * minimal processor state in the event of a machine check or initialization
1327 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1338 /* Return the memory attributes implemented by the processor */
1349 /* Return the amount of memory needed for second phase of processor
1350 * self-test and the required alignment of memory.
1384 pm_info->ppmi_data = iprv.v0; in ia64_pal_perf_mon_info()
1388 /* Specifies the physical address of the processor interrupt block
1409 /* Provide information about configurable processor features */
1426 /* Enable/disable processor dependent features */
1454 return -1; in ia64_get_ptce()
1458 ptce->base = iprv.v0; in ia64_get_ptce()
1459 ptce->count[0] = iprv.v1 >> 32; in ia64_get_ptce()
1460 ptce->count[1] = iprv.v1 & 0xffffffff; in ia64_get_ptce()
1461 ptce->stride[0] = iprv.v2 >> 32; in ia64_get_ptce()
1462 ptce->stride[1] = iprv.v2 & 0xffffffff; in ia64_get_ptce()
1489 /* Return information about the register stack and RSE for this processor
1500 hints->ph_data = iprv.v1; in ia64_pal_rse_info()
1505 * Set the current hardware resource sharing policy of the processor
1515 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1517 * This is usually called in IA-32 mode.
1527 /* Perform the second phase of processor self-test. */
1564 pal_min_version->pal_version_val = iprv.v0; in ia64_pal_version()
1567 pal_cur_version->pal_version_val = iprv.v1; in ia64_pal_version()
1593 /* Return information about the virtual memory characteristics of the processor
1602 tc_info->pti_val = iprv.v0; in ia64_pal_vm_info()
1608 /* Get page size information about the virtual memory characteristics of the processor
1649 /* Get summary information about the virtual memory characteristics of the processor
1658 vm_info_1->pvi1_val = iprv.v0; in ia64_pal_vm_summary()
1660 vm_info_2->pvi2_val = iprv.v1; in ia64_pal_vm_summary()
1673 * Returns information about virtual processor features
1705 tr_valid->piv_val = iprv.v0; in ia64_pal_tr_read()
1720 #define PAL_VISIBILITY_INVAL_ARG -2
1721 #define PAL_VISIBILITY_ERROR -3
1739 cpp :8, /* Cores per processor */
1741 ppid :8, /* Physical processor ID */
1780 /* Get information on logical to physical processor mappings. */
1790 mapping->overview.overview_data = iprv.v0; in ia64_pal_logical_to_phys()
1791 mapping->ppli1.ppli1_data = iprv.v1; in ia64_pal_logical_to_phys()
1792 mapping->ppli2.ppli2_data = iprv.v2; in ia64_pal_logical_to_phys()
1805 /* Get information on logical to physical processor mappings. */
1817 info->num_shared = iprv.v0; in ia64_pal_cache_shared_info()
1818 info->ppli1.ppli1_data = iprv.v1; in ia64_pal_cache_shared_info()
1819 info->ppli2.ppli2_data = iprv.v2; in ia64_pal_cache_shared_info()