Lines Matching +full:0 +full:x0000004f
15 #define MSR_EFER 0xc0000080 /* extended feature register */
16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
44 #define MSR_TEST_CTRL 0x00000033
48 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
49 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
57 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
58 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
60 #define MSR_PPIN_CTL 0x0000004e
61 #define MSR_PPIN 0x0000004f
63 #define MSR_IA32_PERFCTR0 0x000000c1
64 #define MSR_IA32_PERFCTR1 0x000000c2
65 #define MSR_FSB_FREQ 0x000000cd
66 #define MSR_PLATFORM_INFO 0x000000ce
70 #define MSR_IA32_UMWAIT_CONTROL 0xe1
71 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
75 * bit[1:0] zero.
77 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
80 #define MSR_IA32_CORE_CAPS 0x000000cf
84 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
91 #define MSR_MTRRcap 0x000000fe
93 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
94 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
156 #define MSR_IA32_FLUSH_CMD 0x0000010b
157 #define L1D_FLUSH BIT(0) /*
162 #define MSR_IA32_BBL_CR_CTL 0x00000119
163 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
165 #define MSR_IA32_TSX_CTRL 0x00000122
166 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
170 #define MSR_IA32_MCU_OPT_CTRL 0x00000123
171 #define RNGDS_MITG_DIS BIT(0)
174 #define MSR_IA32_SYSENTER_CS 0x00000174
175 #define MSR_IA32_SYSENTER_ESP 0x00000175
176 #define MSR_IA32_SYSENTER_EIP 0x00000176
178 #define MSR_IA32_MCG_CAP 0x00000179
179 #define MSR_IA32_MCG_STATUS 0x0000017a
180 #define MSR_IA32_MCG_CTL 0x0000017b
181 #define MSR_IA32_MCG_EXT_CTL 0x000004d0
183 #define MSR_OFFCORE_RSP_0 0x000001a6
184 #define MSR_OFFCORE_RSP_1 0x000001a7
185 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
186 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae
187 #define MSR_TURBO_RATIO_LIMIT2 0x000001af
189 #define MSR_LBR_SELECT 0x000001c8
190 #define MSR_LBR_TOS 0x000001c9
192 #define MSR_IA32_POWER_CTL 0x000001fc
195 #define MSR_LBR_NHM_FROM 0x00000680
196 #define MSR_LBR_NHM_TO 0x000006c0
197 #define MSR_LBR_CORE_FROM 0x00000040
198 #define MSR_LBR_CORE_TO 0x00000060
200 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
205 #define LBR_INFO_CYCLES 0xffff
207 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
209 #define MSR_ARCH_LBR_CTL 0x000014ce
210 #define ARCH_LBR_CTL_LBREN BIT(0)
212 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
214 #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
216 #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
217 #define MSR_ARCH_LBR_DEPTH 0x000014cf
218 #define MSR_ARCH_LBR_FROM_0 0x00001500
219 #define MSR_ARCH_LBR_TO_0 0x00001600
220 #define MSR_ARCH_LBR_INFO_0 0x00001200
222 #define MSR_IA32_PEBS_ENABLE 0x000003f1
223 #define MSR_PEBS_DATA_CFG 0x000003f2
224 #define MSR_IA32_DS_AREA 0x00000600
225 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
226 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
228 #define MSR_IA32_RTIT_CTL 0x00000570
229 #define RTIT_CTL_TRACEEN BIT(0)
244 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
246 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
248 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
250 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
252 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
254 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
256 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
257 #define MSR_IA32_RTIT_STATUS 0x00000571
258 #define RTIT_STATUS_FILTEREN BIT(0)
265 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
266 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
267 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
268 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
269 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
270 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
271 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
272 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
273 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
274 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
275 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
276 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
278 #define MSR_MTRRfix64K_00000 0x00000250
279 #define MSR_MTRRfix16K_80000 0x00000258
280 #define MSR_MTRRfix16K_A0000 0x00000259
281 #define MSR_MTRRfix4K_C0000 0x00000268
282 #define MSR_MTRRfix4K_C8000 0x00000269
283 #define MSR_MTRRfix4K_D0000 0x0000026a
284 #define MSR_MTRRfix4K_D8000 0x0000026b
285 #define MSR_MTRRfix4K_E0000 0x0000026c
286 #define MSR_MTRRfix4K_E8000 0x0000026d
287 #define MSR_MTRRfix4K_F0000 0x0000026e
288 #define MSR_MTRRfix4K_F8000 0x0000026f
289 #define MSR_MTRRdefType 0x000002ff
291 #define MSR_IA32_CR_PAT 0x00000277
293 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
294 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
295 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
296 #define MSR_IA32_LASTINTFROMIP 0x000001dd
297 #define MSR_IA32_LASTINTTOIP 0x000001de
299 #define MSR_IA32_PASID 0x00000d93
303 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
316 #define MSR_PEBS_FRONTEND 0x000003f7
318 #define MSR_IA32_MC0_CTL 0x00000400
319 #define MSR_IA32_MC0_STATUS 0x00000401
320 #define MSR_IA32_MC0_ADDR 0x00000402
321 #define MSR_IA32_MC0_MISC 0x00000403
324 #define MSR_PKG_C3_RESIDENCY 0x000003f8
325 #define MSR_PKG_C6_RESIDENCY 0x000003f9
326 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
327 #define MSR_PKG_C7_RESIDENCY 0x000003fa
328 #define MSR_CORE_C3_RESIDENCY 0x000003fc
329 #define MSR_CORE_C6_RESIDENCY 0x000003fd
330 #define MSR_CORE_C7_RESIDENCY 0x000003fe
331 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
332 #define MSR_PKG_C2_RESIDENCY 0x0000060d
333 #define MSR_PKG_C8_RESIDENCY 0x00000630
334 #define MSR_PKG_C9_RESIDENCY 0x00000631
335 #define MSR_PKG_C10_RESIDENCY 0x00000632
338 #define MSR_PKGC3_IRTL 0x0000060a
339 #define MSR_PKGC6_IRTL 0x0000060b
340 #define MSR_PKGC7_IRTL 0x0000060c
341 #define MSR_PKGC8_IRTL 0x00000633
342 #define MSR_PKGC9_IRTL 0x00000634
343 #define MSR_PKGC10_IRTL 0x00000635
347 #define MSR_RAPL_POWER_UNIT 0x00000606
349 #define MSR_PKG_POWER_LIMIT 0x00000610
350 #define MSR_PKG_ENERGY_STATUS 0x00000611
351 #define MSR_PKG_PERF_STATUS 0x00000613
352 #define MSR_PKG_POWER_INFO 0x00000614
354 #define MSR_DRAM_POWER_LIMIT 0x00000618
355 #define MSR_DRAM_ENERGY_STATUS 0x00000619
356 #define MSR_DRAM_PERF_STATUS 0x0000061b
357 #define MSR_DRAM_POWER_INFO 0x0000061c
359 #define MSR_PP0_POWER_LIMIT 0x00000638
360 #define MSR_PP0_ENERGY_STATUS 0x00000639
361 #define MSR_PP0_POLICY 0x0000063a
362 #define MSR_PP0_PERF_STATUS 0x0000063b
364 #define MSR_PP1_POWER_LIMIT 0x00000640
365 #define MSR_PP1_ENERGY_STATUS 0x00000641
366 #define MSR_PP1_POLICY 0x00000642
368 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
369 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
372 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
373 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
374 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
375 #define MSR_CONFIG_TDP_CONTROL 0x0000064B
376 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
378 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
380 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
381 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659
382 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
383 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
385 #define MSR_CORE_C1_RES 0x00000660
386 #define MSR_MODULE_C6_RES_MS 0x00000664
388 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
389 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
391 #define MSR_ATOM_CORE_RATIOS 0x0000066a
392 #define MSR_ATOM_CORE_VIDS 0x0000066b
393 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
394 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
397 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
398 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
399 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
402 #define MSR_PPERF 0x0000064e
403 #define MSR_PERF_LIMIT_REASONS 0x0000064f
404 #define MSR_PM_ENABLE 0x00000770
405 #define MSR_HWP_CAPABILITIES 0x00000771
406 #define MSR_HWP_REQUEST_PKG 0x00000772
407 #define MSR_HWP_INTERRUPT 0x00000773
408 #define MSR_HWP_REQUEST 0x00000774
409 #define MSR_HWP_STATUS 0x00000777
419 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
420 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
421 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
422 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
425 #define HWP_MIN_PERF(x) (x & 0xff)
426 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
427 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
428 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
429 #define HWP_EPP_PERFORMANCE 0x00
430 #define HWP_EPP_BALANCE_PERFORMANCE 0x80
431 #define HWP_EPP_BALANCE_POWERSAVE 0xC0
432 #define HWP_EPP_POWERSAVE 0xFF
433 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
434 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
437 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
438 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
441 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
442 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
444 #define MSR_AMD64_MC0_MASK 0xc0010044
454 #define MSR_IA32_MC0_CTL2 0x00000280
457 #define MSR_P6_PERFCTR0 0x000000c1
458 #define MSR_P6_PERFCTR1 0x000000c2
459 #define MSR_P6_EVNTSEL0 0x00000186
460 #define MSR_P6_EVNTSEL1 0x00000187
462 #define MSR_KNC_PERFCTR0 0x00000020
463 #define MSR_KNC_PERFCTR1 0x00000021
464 #define MSR_KNC_EVNTSEL0 0x00000028
465 #define MSR_KNC_EVNTSEL1 0x00000029
468 #define MSR_IA32_PMC0 0x000004c1
471 #define MSR_RELOAD_PMC0 0x000014c1
472 #define MSR_RELOAD_FIXED_CTR0 0x00001309
478 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
479 #define MSR_AMD64_TSC_RATIO 0xc0000104
480 #define MSR_AMD64_NB_CFG 0xc001001f
481 #define MSR_AMD64_PATCH_LOADER 0xc0010020
482 #define MSR_AMD_PERF_CTL 0xc0010062
483 #define MSR_AMD_PERF_STATUS 0xc0010063
484 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
485 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
486 #define MSR_AMD64_OSVW_STATUS 0xc0010141
487 #define MSR_AMD_PPIN_CTL 0xc00102f0
488 #define MSR_AMD_PPIN 0xc00102f1
489 #define MSR_AMD64_CPUID_FN_1 0xc0011004
490 #define MSR_AMD64_LS_CFG 0xc0011020
491 #define MSR_AMD64_DC_CFG 0xc0011022
492 #define MSR_AMD64_BU_CFG2 0xc001102a
493 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
494 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
495 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
498 #define MSR_AMD64_IBSOPCTL 0xc0011033
499 #define MSR_AMD64_IBSOPRIP 0xc0011034
500 #define MSR_AMD64_IBSOPDATA 0xc0011035
501 #define MSR_AMD64_IBSOPDATA2 0xc0011036
502 #define MSR_AMD64_IBSOPDATA3 0xc0011037
503 #define MSR_AMD64_IBSDCLINAD 0xc0011038
504 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
507 #define MSR_AMD64_IBSCTL 0xc001103a
508 #define MSR_AMD64_IBSBRTARGET 0xc001103b
509 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
510 #define MSR_AMD64_IBSOPDATA4 0xc001103d
512 #define MSR_AMD64_SEV_ES_GHCB 0xc0010130
513 #define MSR_AMD64_SEV 0xc0010131
514 #define MSR_AMD64_SEV_ENABLED_BIT 0
519 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
522 #define MSR_F17H_IRPERF 0xc00000e9
524 #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
528 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
529 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
530 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
531 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
532 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
533 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
536 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
537 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
538 #define MSR_F15H_PERF_CTL 0xc0010200
546 #define MSR_F15H_PERF_CTR 0xc0010201
554 #define MSR_F15H_NB_PERF_CTL 0xc0010240
555 #define MSR_F15H_NB_PERF_CTR 0xc0010241
556 #define MSR_F15H_PTSC 0xc0010280
557 #define MSR_F15H_IC_CFG 0xc0011021
558 #define MSR_F15H_EX_CFG 0xc001102c
561 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
562 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
563 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
565 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
567 #define MSR_FAM10H_NODE_ID 0xc001100c
568 #define MSR_F10H_DECFG 0xc0011029
573 #define MSR_K8_TOP_MEM1 0xc001001a
574 #define MSR_K8_TOP_MEM2 0xc001001d
575 #define MSR_K8_SYSCFG 0xc0010010
578 #define MSR_K8_INT_PENDING_MSG 0xc0010055
580 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
581 #define MSR_K8_TSEG_ADDR 0xc0010112
582 #define MSR_K8_TSEG_MASK 0xc0010113
583 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
584 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
585 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
588 #define MSR_K7_EVNTSEL0 0xc0010000
589 #define MSR_K7_PERFCTR0 0xc0010004
590 #define MSR_K7_EVNTSEL1 0xc0010001
591 #define MSR_K7_PERFCTR1 0xc0010005
592 #define MSR_K7_EVNTSEL2 0xc0010002
593 #define MSR_K7_PERFCTR2 0xc0010006
594 #define MSR_K7_EVNTSEL3 0xc0010003
595 #define MSR_K7_PERFCTR3 0xc0010007
596 #define MSR_K7_CLK_CTL 0xc001001b
597 #define MSR_K7_HWCR 0xc0010015
598 #define MSR_K7_HWCR_SMMLOCK_BIT 0
602 #define MSR_K7_FID_VID_CTL 0xc0010041
603 #define MSR_K7_FID_VID_STATUS 0xc0010042
606 #define MSR_K6_WHCR 0xc0000082
607 #define MSR_K6_UWCCR 0xc0000085
608 #define MSR_K6_EPMR 0xc0000086
609 #define MSR_K6_PSOR 0xc0000087
610 #define MSR_K6_PFIR 0xc0000088
613 #define MSR_IDT_FCR1 0x00000107
614 #define MSR_IDT_FCR2 0x00000108
615 #define MSR_IDT_FCR3 0x00000109
616 #define MSR_IDT_FCR4 0x0000010a
618 #define MSR_IDT_MCR0 0x00000110
619 #define MSR_IDT_MCR1 0x00000111
620 #define MSR_IDT_MCR2 0x00000112
621 #define MSR_IDT_MCR3 0x00000113
622 #define MSR_IDT_MCR4 0x00000114
623 #define MSR_IDT_MCR5 0x00000115
624 #define MSR_IDT_MCR6 0x00000116
625 #define MSR_IDT_MCR7 0x00000117
626 #define MSR_IDT_MCR_CTRL 0x00000120
629 #define MSR_VIA_FCR 0x00001107
630 #define MSR_VIA_LONGHAUL 0x0000110a
631 #define MSR_VIA_RNG 0x0000110b
632 #define MSR_VIA_BCR2 0x00001147
635 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
636 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
637 #define MSR_TMTA_LRTI_READOUT 0x80868018
638 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
641 #define MSR_IA32_P5_MC_ADDR 0x00000000
642 #define MSR_IA32_P5_MC_TYPE 0x00000001
643 #define MSR_IA32_TSC 0x00000010
644 #define MSR_IA32_PLATFORM_ID 0x00000017
645 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
646 #define MSR_EBC_FREQUENCY_ID 0x0000002c
647 #define MSR_SMI_COUNT 0x00000034
650 #define MSR_IA32_FEAT_CTL 0x0000003a
651 #define FEAT_CTL_LOCKED BIT(0)
656 #define MSR_IA32_TSC_ADJUST 0x0000003b
657 #define MSR_IA32_BNDCFGS 0x00000d90
659 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
661 #define MSR_IA32_XSS 0x00000da0
663 #define MSR_IA32_APICBASE 0x0000001b
666 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
668 #define MSR_IA32_TSCDEADLINE 0x000006e0
670 #define MSR_IA32_UCODE_WRITE 0x00000079
671 #define MSR_IA32_UCODE_REV 0x0000008b
673 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
674 #define MSR_IA32_SMBASE 0x0000009e
676 #define MSR_IA32_PERF_STATUS 0x00000198
677 #define MSR_IA32_PERF_CTL 0x00000199
678 #define INTEL_PERF_CTL_MASK 0xffff
680 #define MSR_IA32_MPERF 0x000000e7
681 #define MSR_IA32_APERF 0x000000e8
683 #define MSR_IA32_THERM_CONTROL 0x0000019a
684 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
686 #define THERM_INT_HIGH_ENABLE (1 << 0)
690 #define MSR_IA32_THERM_STATUS 0x0000019c
692 #define THERM_STATUS_PROCHOT (1 << 0)
695 #define MSR_THERM2_CTL 0x0000019d
699 #define MSR_IA32_MISC_ENABLE 0x000001a0
701 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
703 #define MSR_MISC_FEATURE_CONTROL 0x000001a4
704 #define MSR_MISC_PWR_MGMT 0x000001aa
706 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
707 #define ENERGY_PERF_BIAS_PERFORMANCE 0
713 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
715 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
718 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
720 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
727 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
730 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
737 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
791 #define MSR_MISC_FEATURES_ENABLES 0x00000140
793 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
797 #define MSR_IA32_TSC_DEADLINE 0x000006E0
800 #define MSR_TSX_FORCE_ABORT 0x0000010F
802 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0
806 #define MSR_IA32_MCG_EAX 0x00000180
807 #define MSR_IA32_MCG_EBX 0x00000181
808 #define MSR_IA32_MCG_ECX 0x00000182
809 #define MSR_IA32_MCG_EDX 0x00000183
810 #define MSR_IA32_MCG_ESI 0x00000184
811 #define MSR_IA32_MCG_EDI 0x00000185
812 #define MSR_IA32_MCG_EBP 0x00000186
813 #define MSR_IA32_MCG_ESP 0x00000187
814 #define MSR_IA32_MCG_EFLAGS 0x00000188
815 #define MSR_IA32_MCG_EIP 0x00000189
816 #define MSR_IA32_MCG_RESERVED 0x0000018a
819 #define MSR_P4_BPU_PERFCTR0 0x00000300
820 #define MSR_P4_BPU_PERFCTR1 0x00000301
821 #define MSR_P4_BPU_PERFCTR2 0x00000302
822 #define MSR_P4_BPU_PERFCTR3 0x00000303
823 #define MSR_P4_MS_PERFCTR0 0x00000304
824 #define MSR_P4_MS_PERFCTR1 0x00000305
825 #define MSR_P4_MS_PERFCTR2 0x00000306
826 #define MSR_P4_MS_PERFCTR3 0x00000307
827 #define MSR_P4_FLAME_PERFCTR0 0x00000308
828 #define MSR_P4_FLAME_PERFCTR1 0x00000309
829 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
830 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
831 #define MSR_P4_IQ_PERFCTR0 0x0000030c
832 #define MSR_P4_IQ_PERFCTR1 0x0000030d
833 #define MSR_P4_IQ_PERFCTR2 0x0000030e
834 #define MSR_P4_IQ_PERFCTR3 0x0000030f
835 #define MSR_P4_IQ_PERFCTR4 0x00000310
836 #define MSR_P4_IQ_PERFCTR5 0x00000311
837 #define MSR_P4_BPU_CCCR0 0x00000360
838 #define MSR_P4_BPU_CCCR1 0x00000361
839 #define MSR_P4_BPU_CCCR2 0x00000362
840 #define MSR_P4_BPU_CCCR3 0x00000363
841 #define MSR_P4_MS_CCCR0 0x00000364
842 #define MSR_P4_MS_CCCR1 0x00000365
843 #define MSR_P4_MS_CCCR2 0x00000366
844 #define MSR_P4_MS_CCCR3 0x00000367
845 #define MSR_P4_FLAME_CCCR0 0x00000368
846 #define MSR_P4_FLAME_CCCR1 0x00000369
847 #define MSR_P4_FLAME_CCCR2 0x0000036a
848 #define MSR_P4_FLAME_CCCR3 0x0000036b
849 #define MSR_P4_IQ_CCCR0 0x0000036c
850 #define MSR_P4_IQ_CCCR1 0x0000036d
851 #define MSR_P4_IQ_CCCR2 0x0000036e
852 #define MSR_P4_IQ_CCCR3 0x0000036f
853 #define MSR_P4_IQ_CCCR4 0x00000370
854 #define MSR_P4_IQ_CCCR5 0x00000371
855 #define MSR_P4_ALF_ESCR0 0x000003ca
856 #define MSR_P4_ALF_ESCR1 0x000003cb
857 #define MSR_P4_BPU_ESCR0 0x000003b2
858 #define MSR_P4_BPU_ESCR1 0x000003b3
859 #define MSR_P4_BSU_ESCR0 0x000003a0
860 #define MSR_P4_BSU_ESCR1 0x000003a1
861 #define MSR_P4_CRU_ESCR0 0x000003b8
862 #define MSR_P4_CRU_ESCR1 0x000003b9
863 #define MSR_P4_CRU_ESCR2 0x000003cc
864 #define MSR_P4_CRU_ESCR3 0x000003cd
865 #define MSR_P4_CRU_ESCR4 0x000003e0
866 #define MSR_P4_CRU_ESCR5 0x000003e1
867 #define MSR_P4_DAC_ESCR0 0x000003a8
868 #define MSR_P4_DAC_ESCR1 0x000003a9
869 #define MSR_P4_FIRM_ESCR0 0x000003a4
870 #define MSR_P4_FIRM_ESCR1 0x000003a5
871 #define MSR_P4_FLAME_ESCR0 0x000003a6
872 #define MSR_P4_FLAME_ESCR1 0x000003a7
873 #define MSR_P4_FSB_ESCR0 0x000003a2
874 #define MSR_P4_FSB_ESCR1 0x000003a3
875 #define MSR_P4_IQ_ESCR0 0x000003ba
876 #define MSR_P4_IQ_ESCR1 0x000003bb
877 #define MSR_P4_IS_ESCR0 0x000003b4
878 #define MSR_P4_IS_ESCR1 0x000003b5
879 #define MSR_P4_ITLB_ESCR0 0x000003b6
880 #define MSR_P4_ITLB_ESCR1 0x000003b7
881 #define MSR_P4_IX_ESCR0 0x000003c8
882 #define MSR_P4_IX_ESCR1 0x000003c9
883 #define MSR_P4_MOB_ESCR0 0x000003aa
884 #define MSR_P4_MOB_ESCR1 0x000003ab
885 #define MSR_P4_MS_ESCR0 0x000003c0
886 #define MSR_P4_MS_ESCR1 0x000003c1
887 #define MSR_P4_PMH_ESCR0 0x000003ac
888 #define MSR_P4_PMH_ESCR1 0x000003ad
889 #define MSR_P4_RAT_ESCR0 0x000003bc
890 #define MSR_P4_RAT_ESCR1 0x000003bd
891 #define MSR_P4_SAAT_ESCR0 0x000003ae
892 #define MSR_P4_SAAT_ESCR1 0x000003af
893 #define MSR_P4_SSU_ESCR0 0x000003be
894 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
896 #define MSR_P4_TBPU_ESCR0 0x000003c2
897 #define MSR_P4_TBPU_ESCR1 0x000003c3
898 #define MSR_P4_TC_ESCR0 0x000003c4
899 #define MSR_P4_TC_ESCR1 0x000003c5
900 #define MSR_P4_U2L_ESCR0 0x000003b0
901 #define MSR_P4_U2L_ESCR1 0x000003b1
903 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
906 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
907 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
908 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
909 #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c
910 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
911 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
912 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
913 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
915 #define MSR_PERF_METRICS 0x00000329
926 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
929 #define MSR_IA32_VMX_BASIC 0x00000480
930 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
931 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
932 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
933 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
934 #define MSR_IA32_VMX_MISC 0x00000485
935 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
936 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
937 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
938 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
939 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
940 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
941 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
942 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
943 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
944 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
945 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
946 #define MSR_IA32_VMX_VMFUNC 0x00000491
951 #define VMX_BASIC_64 0x0001000000000000LLU
953 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
955 #define VMX_BASIC_INOUT 0x0040000000000000LLU
960 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
963 #define MSR_VM_CR 0xc0010114
964 #define MSR_VM_IGNNE 0xc0010115
965 #define MSR_VM_HSAVE_PA 0xc0010117