Lines Matching full:rw

106 #define SUNI_MRI_RESET		0x80	/* RW, reset & power down chip
115 #define SUNI_MCT_LOOPT		0x01	/* RW, timing source, 0: from
117 #define SUNI_MCT_DLE		0x02	/* RW, diagnostic loopback */
118 #define SUNI_MCT_LLE		0x04	/* RW, line loopback */
119 #define SUNI_MCT_FIXPTR		0x20	/* RW, disable transmit payload pointer
125 #define SUNI_MCT_LCDE		0x80	/* RW, loss of cell delineation
128 #define SUNI_RSOP_CIE_OOFE	0x01	/* RW, enable interrupt on frame alarm
130 #define SUNI_RSOP_CIE_LOFE	0x02	/* RW, enable interrupt on loss of
132 #define SUNI_RSOP_CIE_LOSE	0x04	/* RW, enable interrupt on loss of
134 #define SUNI_RSOP_CIE_BIPEE	0x08	/* RW, enable interrupt on section
138 #define SUNI_RSOP_CIE_DDS	0x40	/* RW, disable scrambling */
172 #define SUNI_TPOP_APM_APTR	0x03	/* RW, arbitrary pointer, upper 2
175 #define SUNI_TPOP_APM_S		0x0c	/* RW, "unused" bits of payload
178 #define SUNI_TPOP_APM_NDF	0xf0	 /* RW, NDF bits */
190 #define SUNI_RACP_IES_FIFOE	0x20	/* RW, enable FIFO overrun interrupt */
191 #define SUNI_RACP_IES_HCSE	0x40	/* RW, enable HCS error interrupt */
192 #define SUNI_RACP_IES_OOCDE	0x80	/* RW, enable cell delineation state
196 #define SUNI_TACP_CS_FIFORST	0x01	/* RW, reset transmit FIFO (sticky) */
197 #define SUNI_TACP_CS_DSCR	0x02	/* RW, disable payload scrambling */
198 #define SUNI_TACP_CS_HCAADD	0x04	/* RW, add coset polynomial to HCS */
199 #define SUNI_TACP_CS_DHCS	0x10	/* RW, insert HCS errors */
202 #define SUNI_TACP_CS_FIFOE	0x80	/* RW, enable FIFO overrun interrupt */
205 #define SUNI_TACP_IUCHP_CLP	0x01	/* RW, 8th bit of 4th octet of i/u
207 #define SUNI_TACP_IUCHP_PTI	0x0e	/* RW, 5th-7th bits of 4th octet of i/u
210 #define SUNI_TACP_IUCHP_GFC	0xf0	/* RW, 1st-4th bits of 1st octet of i/u
218 #define SUNI_MT_HIZIO		0x01	/* RW, all but data bus & MP interface
221 #define SUNI_MT_IOTST		0x04	/* RW, enable test mode */
224 #define SUNI_MT_DS27_53		0x80	/* RW, select between 8- or 16- bit */