1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
12  * pll v1
16  * @base	base address of pll registers
18  * PLL clock version 1, found on i.MX1/21/25/27/31/35
22 #define MFN_SIGN	(BIT(MFN_BITS - 1))
23 #define MFN_MASK	(MFN_SIGN - 1)
33 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll)  in is_imx1_pllv1()  argument
35 	return pll->type == IMX_PLLV1_IMX1;  in is_imx1_pllv1()
38 static inline bool is_imx21_pllv1(struct clk_pllv1 *pll)  in is_imx21_pllv1()  argument
40 	return pll->type == IMX_PLLV1_IMX21;  in is_imx21_pllv1()
43 static inline bool is_imx27_pllv1(struct clk_pllv1 *pll)  in is_imx27_pllv1()  argument
45 	return pll->type == IMX_PLLV1_IMX27;  in is_imx27_pllv1()
48 static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn)  in mfn_is_negative()  argument
50 	return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN);  in mfn_is_negative()
56 	struct clk_pllv1 *pll = to_clk_pllv1(hw);  in clk_pllv1_recalc_rate()  local
63 	reg = readl(pll->base);  in clk_pllv1_recalc_rate()
66 	 * Get the resulting clock rate from a PLL register value and the input  in clk_pllv1_recalc_rate()
70 	 *                  mfi + mfn / (mfd + 1)  in clk_pllv1_recalc_rate()
71 	 *  f = 2 * f_ref * --------------------  in clk_pllv1_recalc_rate()
72 	 *                        pd + 1  in clk_pllv1_recalc_rate()
89 	if (mfn_is_negative(pll, mfn)) {  in clk_pllv1_recalc_rate()
90 		if (is_imx27_pllv1(pll))  in clk_pllv1_recalc_rate()
93 			mfn_abs = BIT(MFN_BITS) - mfn;  in clk_pllv1_recalc_rate()
97 	rate /= pd + 1;  in clk_pllv1_recalc_rate()
101 	do_div(ull, mfd + 1);  in clk_pllv1_recalc_rate()
103 	if (mfn_is_negative(pll, mfn))  in clk_pllv1_recalc_rate()
104 		ull = (rate * mfi) - ull;  in clk_pllv1_recalc_rate()
118 	struct clk_pllv1 *pll;  in imx_clk_hw_pllv1()  local
123 	pll = kmalloc(sizeof(*pll), GFP_KERNEL);  in imx_clk_hw_pllv1()
124 	if (!pll)  in imx_clk_hw_pllv1()
125 		return ERR_PTR(-ENOMEM);  in imx_clk_hw_pllv1()
127 	pll->base = base;  in imx_clk_hw_pllv1()
128 	pll->type = type;  in imx_clk_hw_pllv1()
134 	init.num_parents = 1;  in imx_clk_hw_pllv1()
136 	pll->hw.init = &init;  in imx_clk_hw_pllv1()
137 	hw = &pll->hw;  in imx_clk_hw_pllv1()
141 		kfree(pll);  in imx_clk_hw_pllv1()