Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-AXG Clock Controller Driver
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
15 #include "meson-aoclk.h"
16 #include "g12a-aoclk.h"
18 #include "clk-regmap.h"
19 #include "clk-dualdiv.h"
23 * Register offsets from the data sheet must be multiplied by 4.
45 .data = &(struct clk_regmap_gate_data) { \
53 .fw_name = "mpeg-clk", \
77 .data = &(struct clk_regmap_gate_data){
104 .data = &(struct clk_regmap_gate_data){
119 .data = &(struct meson_clk_dualdiv_data){
122 .shift = 0,
127 .shift = 12,
132 .shift = 0,
137 .shift = 12,
142 .shift = 28,
158 .data = &(struct clk_regmap_mux_data) {
161 .shift = 24,
177 .data = &(struct clk_regmap_gate_data){
195 .data = &(struct clk_regmap_gate_data){
210 .data = &(struct meson_clk_dualdiv_data){
213 .shift = 0,
218 .shift = 12,
223 .shift = 0,
228 .shift = 12,
233 .shift = 28,
249 .data = &(struct clk_regmap_mux_data) {
252 .shift = 24,
268 .data = &(struct clk_regmap_gate_data){
284 .data = &(struct clk_regmap_mux_data) {
287 .shift = 10,
295 { .fw_name = "ext-32k-0", },
303 .data = &(struct clk_regmap_mux_data) {
306 .shift = 8,
313 { .fw_name = "mpeg-clk", },
322 .data = &(struct clk_regmap_mux_data) {
325 .shift = 9,
339 .data = &(struct clk_regmap_div_data) {
341 .shift = 0,
356 .data = &(struct clk_regmap_gate_data) {
459 .compatible = "amlogic,meson-g12a-aoclkc",
460 .data = &g12a_aoclkc_data,
468 .name = "g12a-aoclkc",