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Lines Matching +full:init +full:- +full:delay

1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
31 #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
44 if (!(gate->flags & TEGRA_PERIPH_NO_RESET)) in clk_periph_is_enabled()
58 if (!(gate->flags & TEGRA_PERIPH_NO_RESET) && in clk_periph_enable_locked()
59 !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) { in clk_periph_enable_locked()
61 udelay(5); /* reset propogation delay */ in clk_periph_enable_locked()
66 if (gate->flags & TEGRA_PERIPH_WAR_1005168) { in clk_periph_enable_locked()
67 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
68 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
70 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
83 if (gate->flags & TEGRA_PERIPH_ON_APB) in clk_periph_disable_locked()
96 if (!gate->enable_refcnt[gate->clk_num]++) in clk_periph_enable()
111 WARN_ON(!gate->enable_refcnt[gate->clk_num]); in clk_periph_disable()
113 if (--gate->enable_refcnt[gate->clk_num] == 0) in clk_periph_disable()
129 * be non-zero here if the "unused" duplicate is disabled by CCF. in clk_periph_disable_unused()
131 if (!gate->enable_refcnt[gate->clk_num]) in clk_periph_disable_unused()
150 struct clk_init_data init; in tegra_clk_register_periph_gate() local
155 return ERR_PTR(-EINVAL); in tegra_clk_register_periph_gate()
160 return ERR_PTR(-ENOMEM); in tegra_clk_register_periph_gate()
163 init.name = name; in tegra_clk_register_periph_gate()
164 init.flags = flags; in tegra_clk_register_periph_gate()
165 init.parent_names = parent_name ? &parent_name : NULL; in tegra_clk_register_periph_gate()
166 init.num_parents = parent_name ? 1 : 0; in tegra_clk_register_periph_gate()
167 init.ops = &tegra_clk_periph_gate_ops; in tegra_clk_register_periph_gate()
169 gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC; in tegra_clk_register_periph_gate()
170 gate->clk_base = clk_base; in tegra_clk_register_periph_gate()
171 gate->clk_num = clk_num; in tegra_clk_register_periph_gate()
172 gate->flags = gate_flags; in tegra_clk_register_periph_gate()
173 gate->enable_refcnt = enable_refcnt; in tegra_clk_register_periph_gate()
174 gate->regs = pregs; in tegra_clk_register_periph_gate()
176 /* Data in .init is copied by clk_register(), so stack variable OK */ in tegra_clk_register_periph_gate()
177 gate->hw.init = &init; in tegra_clk_register_periph_gate()
179 clk = clk_register(NULL, &gate->hw); in tegra_clk_register_periph_gate()