Lines Matching +full:max +full:- +full:clk +full:- +full:rate +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
8 #include <linux/clk.h>
56 static int __init pit_clocksource_init(unsigned long rate) in pit_clocksource_init() argument
58 /* set the max load value and start the clock source counter */ in pit_clocksource_init()
63 sched_clock_register(pit_read_sched_clock, 32, rate); in pit_clocksource_init()
64 return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, in pit_clocksource_init()
79 __raw_writel(delta - 1, clkevt_base + PITLDVAL); in pit_set_next_event()
112 evt->event_handler(evt); in pit_timer_interrupt()
126 static int __init pit_clockevent_init(unsigned long rate, int irq) in pit_clockevent_init() argument
138 * LDVAL trigger = (period / clock period) - 1 in pit_clockevent_init()
139 * The pit is a 32-bit down count timer, when the conter value in pit_clockevent_init()
142 * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit. in pit_clockevent_init()
144 clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff); in pit_clockevent_init()
151 struct clk *pit_clk; in pit_timer_init()
159 return -ENXIO; in pit_timer_init()
163 * PIT0 and PIT1 can be chained to build a 64-bit timer, in pit_timer_init()
172 return -EINVAL; in pit_timer_init()
183 cycle_per_jiffy = clk_rate / (HZ); in pit_timer_init()
194 TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);