Lines Matching +full:stream +full:- +full:match +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
9 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
15 #include <linux/dma-mapping.h>
31 #include "virt-dma.h"
47 /* DMA Stream x Configuration Register */
74 #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */
83 /* DMA Stream x number of data register */
86 /* DMA stream peripheral address register */
89 /* DMA stream x memory 0 address register */
92 /* DMA stream x memory 1 address register */
95 /* DMA stream x FIFO control register */
158 * struct stm32_dma_cfg - STM32 DMA custom configuration
161 * @stream_config: 32bit mask specifying the DMA channel configuration
162 * @features: 32bit mask specifying the DMA Feature list
221 return container_of(chan->vchan.chan.device, struct stm32_dma_device, in stm32_dma_get_dev()
237 return &chan->vchan.chan.dev->device; in chan2dev()
242 return readl_relaxed(dmadev->base + reg); in stm32_dma_read()
247 writel_relaxed(val, dmadev->base + reg); in stm32_dma_write()
262 return -EINVAL; in stm32_dma_get_width()
358 return -EINVAL; in stm32_dma_get_burst()
365 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; in stm32_dma_set_fifo_config()
366 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
370 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
373 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; in stm32_dma_set_fifo_config()
382 memcpy(&chan->dma_sconfig, config, sizeof(*config)); in stm32_dma_slave_config()
384 chan->config_init = true; in stm32_dma_slave_config()
398 * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. in stm32_dma_irq_status()
399 * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. in stm32_dma_irq_status()
402 if (chan->id & 4) in stm32_dma_irq_status()
407 flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); in stm32_dma_irq_status()
421 * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. in stm32_dma_irq_clear()
422 * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. in stm32_dma_irq_clear()
425 dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); in stm32_dma_irq_clear()
427 if (chan->id & 4) in stm32_dma_irq_clear()
438 id = chan->id; in stm32_dma_disable_chan()
446 return readl_relaxed_poll_timeout_atomic(dmadev->base + reg, in stm32_dma_disable_chan()
461 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_stop()
463 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_stop()
464 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_stop()
466 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); in stm32_dma_stop()
481 chan->busy = false; in stm32_dma_stop()
490 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_terminate_all()
492 if (chan->desc) { in stm32_dma_terminate_all()
493 vchan_terminate_vdesc(&chan->desc->vdesc); in stm32_dma_terminate_all()
494 if (chan->busy) in stm32_dma_terminate_all()
496 chan->desc = NULL; in stm32_dma_terminate_all()
499 vchan_get_all_descriptors(&chan->vchan, &head); in stm32_dma_terminate_all()
500 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_terminate_all()
501 vchan_dma_desc_free_list(&chan->vchan, &head); in stm32_dma_terminate_all()
510 vchan_synchronize(&chan->vchan); in stm32_dma_synchronize()
516 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_dump_reg()
517 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_dump_reg()
518 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); in stm32_dma_dump_reg()
519 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); in stm32_dma_dump_reg()
520 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); in stm32_dma_dump_reg()
521 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_dump_reg()
546 if (!chan->desc) { in stm32_dma_start_transfer()
547 vdesc = vchan_next_desc(&chan->vchan); in stm32_dma_start_transfer()
551 list_del(&vdesc->node); in stm32_dma_start_transfer()
553 chan->desc = to_stm32_dma_desc(vdesc); in stm32_dma_start_transfer()
554 chan->next_sg = 0; in stm32_dma_start_transfer()
557 if (chan->next_sg == chan->desc->num_sgs) in stm32_dma_start_transfer()
558 chan->next_sg = 0; in stm32_dma_start_transfer()
560 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_start_transfer()
561 reg = &sg_req->chan_reg; in stm32_dma_start_transfer()
563 reg->dma_scr &= ~STM32_DMA_SCR_EN; in stm32_dma_start_transfer()
564 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
565 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); in stm32_dma_start_transfer()
566 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); in stm32_dma_start_transfer()
567 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); in stm32_dma_start_transfer()
568 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); in stm32_dma_start_transfer()
569 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); in stm32_dma_start_transfer()
571 chan->next_sg++; in stm32_dma_start_transfer()
578 if (chan->desc->cyclic) in stm32_dma_start_transfer()
584 reg->dma_scr |= STM32_DMA_SCR_EN; in stm32_dma_start_transfer()
585 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
587 chan->busy = true; in stm32_dma_start_transfer()
589 dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); in stm32_dma_start_transfer()
598 id = chan->id; in stm32_dma_configure_next_sg()
602 if (chan->next_sg == chan->desc->num_sgs) in stm32_dma_configure_next_sg()
603 chan->next_sg = 0; in stm32_dma_configure_next_sg()
605 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_configure_next_sg()
608 dma_sm0ar = sg_req->chan_reg.dma_sm0ar; in stm32_dma_configure_next_sg()
613 dma_sm1ar = sg_req->chan_reg.dma_sm1ar; in stm32_dma_configure_next_sg()
623 if (chan->desc) { in stm32_dma_handle_chan_done()
624 if (chan->desc->cyclic) { in stm32_dma_handle_chan_done()
625 vchan_cyclic_callback(&chan->desc->vdesc); in stm32_dma_handle_chan_done()
626 chan->next_sg++; in stm32_dma_handle_chan_done()
629 chan->busy = false; in stm32_dma_handle_chan_done()
630 if (chan->next_sg == chan->desc->num_sgs) { in stm32_dma_handle_chan_done()
631 vchan_cookie_complete(&chan->desc->vdesc); in stm32_dma_handle_chan_done()
632 chan->desc = NULL; in stm32_dma_handle_chan_done()
645 spin_lock(&chan->vchan.lock); in stm32_dma_chan_irq()
648 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_chan_irq()
649 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_chan_irq()
684 spin_unlock(&chan->vchan.lock); in stm32_dma_chan_irq()
694 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_issue_pending()
695 if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { in stm32_dma_issue_pending()
696 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); in stm32_dma_issue_pending()
700 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_issue_pending()
714 src_addr_width = chan->dma_sconfig.src_addr_width; in stm32_dma_set_xfer_param()
715 dst_addr_width = chan->dma_sconfig.dst_addr_width; in stm32_dma_set_xfer_param()
716 src_maxburst = chan->dma_sconfig.src_maxburst; in stm32_dma_set_xfer_param()
717 dst_maxburst = chan->dma_sconfig.dst_maxburst; in stm32_dma_set_xfer_param()
718 fifoth = chan->threshold; in stm32_dma_set_xfer_param()
739 chan->mem_width = src_addr_width; in stm32_dma_set_xfer_param()
761 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; in stm32_dma_set_xfer_param()
763 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); in stm32_dma_set_xfer_param()
766 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; in stm32_dma_set_xfer_param()
781 chan->mem_burst = src_best_burst; in stm32_dma_set_xfer_param()
788 chan->mem_width = dst_addr_width; in stm32_dma_set_xfer_param()
799 chan->mem_burst = dst_best_burst; in stm32_dma_set_xfer_param()
811 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; in stm32_dma_set_xfer_param()
813 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); in stm32_dma_set_xfer_param()
816 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; in stm32_dma_set_xfer_param()
817 *buswidth = chan->dma_sconfig.src_addr_width; in stm32_dma_set_xfer_param()
822 return -EINVAL; in stm32_dma_set_xfer_param()
828 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | in stm32_dma_set_xfer_param()
831 chan->chan_reg.dma_scr |= dma_scr; in stm32_dma_set_xfer_param()
853 if (!chan->config_init) { in stm32_dma_prep_slave_sg()
868 if (chan->dma_sconfig.device_fc) in stm32_dma_prep_slave_sg()
869 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
871 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
879 desc->sg_req[i].len = sg_dma_len(sg); in stm32_dma_prep_slave_sg()
881 nb_data_items = desc->sg_req[i].len / buswidth; in stm32_dma_prep_slave_sg()
887 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); in stm32_dma_prep_slave_sg()
888 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_slave_sg()
889 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; in stm32_dma_prep_slave_sg()
890 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; in stm32_dma_prep_slave_sg()
891 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg); in stm32_dma_prep_slave_sg()
892 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg); in stm32_dma_prep_slave_sg()
893 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; in stm32_dma_prep_slave_sg()
896 desc->num_sgs = sg_len; in stm32_dma_prep_slave_sg()
897 desc->cyclic = false; in stm32_dma_prep_slave_sg()
899 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_slave_sg()
922 if (!chan->config_init) { in stm32_dma_prep_dma_cyclic()
938 if (chan->busy) { in stm32_dma_prep_dma_cyclic()
955 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; in stm32_dma_prep_dma_cyclic()
957 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_prep_dma_cyclic()
960 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_dma_cyclic()
969 desc->sg_req[i].len = period_len; in stm32_dma_prep_dma_cyclic()
971 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); in stm32_dma_prep_dma_cyclic()
972 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_dma_cyclic()
973 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; in stm32_dma_prep_dma_cyclic()
974 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; in stm32_dma_prep_dma_cyclic()
975 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr; in stm32_dma_prep_dma_cyclic()
976 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr; in stm32_dma_prep_dma_cyclic()
977 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; in stm32_dma_prep_dma_cyclic()
981 desc->num_sgs = num_periods; in stm32_dma_prep_dma_cyclic()
982 desc->cyclic = true; in stm32_dma_prep_dma_cyclic()
984 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_dma_cyclic()
1003 threshold = chan->threshold; in stm32_dma_prep_dma_memcpy()
1006 xfer_count = min_t(size_t, len - offset, in stm32_dma_prep_dma_memcpy()
1015 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); in stm32_dma_prep_dma_memcpy()
1016 desc->sg_req[i].chan_reg.dma_scr = in stm32_dma_prep_dma_memcpy()
1024 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; in stm32_dma_prep_dma_memcpy()
1025 desc->sg_req[i].chan_reg.dma_sfcr |= in stm32_dma_prep_dma_memcpy()
1027 desc->sg_req[i].chan_reg.dma_spar = src + offset; in stm32_dma_prep_dma_memcpy()
1028 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset; in stm32_dma_prep_dma_memcpy()
1029 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count; in stm32_dma_prep_dma_memcpy()
1030 desc->sg_req[i].len = xfer_count; in stm32_dma_prep_dma_memcpy()
1033 desc->num_sgs = num_sgs; in stm32_dma_prep_dma_memcpy()
1034 desc->cyclic = false; in stm32_dma_prep_dma_memcpy()
1036 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_dma_memcpy()
1044 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_get_remaining_bytes()
1046 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_get_remaining_bytes()
1052 * stm32_dma_is_current_sg - check that expected sg_req is currently transferred
1069 id = chan->id; in stm32_dma_is_current_sg()
1075 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_is_current_sg()
1079 return (dma_smar == sg_req->chan_reg.dma_sm0ar); in stm32_dma_is_current_sg()
1084 return (dma_smar == sg_req->chan_reg.dma_sm1ar); in stm32_dma_is_current_sg()
1094 struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_desc_residue()
1100 * - the sg_req currently transferred in stm32_dma_desc_residue()
1101 * - the Hardware remaining position in this sg (NDTR bits field). in stm32_dma_desc_residue()
1111 * - read the SxNDTR register in stm32_dma_desc_residue()
1112 * - crosscheck that hardware is still in current transfer. in stm32_dma_desc_residue()
1126 if (n_sg == chan->desc->num_sgs) in stm32_dma_desc_residue()
1128 residue = sg_req->len; in stm32_dma_desc_residue()
1138 if (!chan->desc->cyclic || n_sg != 0) in stm32_dma_desc_residue()
1139 for (i = n_sg; i < desc->num_sgs; i++) in stm32_dma_desc_residue()
1140 residue += desc->sg_req[i].len; in stm32_dma_desc_residue()
1142 if (!chan->mem_burst) in stm32_dma_desc_residue()
1145 burst_size = chan->mem_burst * chan->mem_width; in stm32_dma_desc_residue()
1148 residue = residue - modulo + burst_size; in stm32_dma_desc_residue()
1167 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_tx_status()
1168 vdesc = vchan_find_desc(&chan->vchan, cookie); in stm32_dma_tx_status()
1169 if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) in stm32_dma_tx_status()
1170 residue = stm32_dma_desc_residue(chan, chan->desc, in stm32_dma_tx_status()
1171 chan->next_sg); in stm32_dma_tx_status()
1177 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_tx_status()
1188 chan->config_init = false; in stm32_dma_alloc_chan_resources()
1190 ret = pm_runtime_resume_and_get(dmadev->ddev.dev); in stm32_dma_alloc_chan_resources()
1196 pm_runtime_put(dmadev->ddev.dev); in stm32_dma_alloc_chan_resources()
1207 dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); in stm32_dma_free_chan_resources()
1209 if (chan->busy) { in stm32_dma_free_chan_resources()
1210 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_free_chan_resources()
1212 chan->desc = NULL; in stm32_dma_free_chan_resources()
1213 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_free_chan_resources()
1216 pm_runtime_put(dmadev->ddev.dev); in stm32_dma_free_chan_resources()
1229 stm32_dma_clear_reg(&chan->chan_reg); in stm32_dma_set_config()
1231 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; in stm32_dma_set_config()
1232 chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line); in stm32_dma_set_config()
1235 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; in stm32_dma_set_config()
1237 chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features); in stm32_dma_set_config()
1238 if (STM32_DMA_DIRECT_MODE_GET(cfg->features)) in stm32_dma_set_config()
1239 chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE; in stm32_dma_set_config()
1245 struct stm32_dma_device *dmadev = ofdma->of_dma_data; in stm32_dma_of_xlate()
1246 struct device *dev = dmadev->ddev.dev; in stm32_dma_of_xlate()
1251 if (dma_spec->args_count < 4) { in stm32_dma_of_xlate()
1256 cfg.channel_id = dma_spec->args[0]; in stm32_dma_of_xlate()
1257 cfg.request_line = dma_spec->args[1]; in stm32_dma_of_xlate()
1258 cfg.stream_config = dma_spec->args[2]; in stm32_dma_of_xlate()
1259 cfg.features = dma_spec->args[3]; in stm32_dma_of_xlate()
1267 chan = &dmadev->chan[cfg.channel_id]; in stm32_dma_of_xlate()
1269 c = dma_get_slave_channel(&chan->vchan.chan); in stm32_dma_of_xlate()
1281 { .compatible = "st,stm32-dma", },
1291 const struct of_device_id *match; in stm32_dma_probe() local
1296 match = of_match_device(stm32_dma_of_match, &pdev->dev); in stm32_dma_probe()
1297 if (!match) { in stm32_dma_probe()
1298 dev_err(&pdev->dev, "Error: No device match found\n"); in stm32_dma_probe()
1299 return -ENODEV; in stm32_dma_probe()
1302 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL); in stm32_dma_probe()
1304 return -ENOMEM; in stm32_dma_probe()
1306 dd = &dmadev->ddev; in stm32_dma_probe()
1309 dmadev->base = devm_ioremap_resource(&pdev->dev, res); in stm32_dma_probe()
1310 if (IS_ERR(dmadev->base)) in stm32_dma_probe()
1311 return PTR_ERR(dmadev->base); in stm32_dma_probe()
1313 dmadev->clk = devm_clk_get(&pdev->dev, NULL); in stm32_dma_probe()
1314 if (IS_ERR(dmadev->clk)) in stm32_dma_probe()
1315 return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n"); in stm32_dma_probe()
1317 ret = clk_prepare_enable(dmadev->clk); in stm32_dma_probe()
1319 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret); in stm32_dma_probe()
1323 dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node, in stm32_dma_probe()
1326 rst = devm_reset_control_get(&pdev->dev, NULL); in stm32_dma_probe()
1329 if (ret == -EPROBE_DEFER) in stm32_dma_probe()
1337 dma_set_max_seg_size(&pdev->dev, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); in stm32_dma_probe()
1339 dma_cap_set(DMA_SLAVE, dd->cap_mask); in stm32_dma_probe()
1340 dma_cap_set(DMA_PRIVATE, dd->cap_mask); in stm32_dma_probe()
1341 dma_cap_set(DMA_CYCLIC, dd->cap_mask); in stm32_dma_probe()
1342 dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources; in stm32_dma_probe()
1343 dd->device_free_chan_resources = stm32_dma_free_chan_resources; in stm32_dma_probe()
1344 dd->device_tx_status = stm32_dma_tx_status; in stm32_dma_probe()
1345 dd->device_issue_pending = stm32_dma_issue_pending; in stm32_dma_probe()
1346 dd->device_prep_slave_sg = stm32_dma_prep_slave_sg; in stm32_dma_probe()
1347 dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic; in stm32_dma_probe()
1348 dd->device_config = stm32_dma_slave_config; in stm32_dma_probe()
1349 dd->device_terminate_all = stm32_dma_terminate_all; in stm32_dma_probe()
1350 dd->device_synchronize = stm32_dma_synchronize; in stm32_dma_probe()
1351 dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | in stm32_dma_probe()
1354 dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | in stm32_dma_probe()
1357 dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in stm32_dma_probe()
1358 dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in stm32_dma_probe()
1359 dd->copy_align = DMAENGINE_ALIGN_32_BYTES; in stm32_dma_probe()
1360 dd->max_burst = STM32_DMA_MAX_BURST; in stm32_dma_probe()
1361 dd->descriptor_reuse = true; in stm32_dma_probe()
1362 dd->dev = &pdev->dev; in stm32_dma_probe()
1363 INIT_LIST_HEAD(&dd->channels); in stm32_dma_probe()
1365 if (dmadev->mem2mem) { in stm32_dma_probe()
1366 dma_cap_set(DMA_MEMCPY, dd->cap_mask); in stm32_dma_probe()
1367 dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy; in stm32_dma_probe()
1368 dd->directions |= BIT(DMA_MEM_TO_MEM); in stm32_dma_probe()
1372 chan = &dmadev->chan[i]; in stm32_dma_probe()
1373 chan->id = i; in stm32_dma_probe()
1374 chan->vchan.desc_free = stm32_dma_desc_free; in stm32_dma_probe()
1375 vchan_init(&chan->vchan, dd); in stm32_dma_probe()
1383 chan = &dmadev->chan[i]; in stm32_dma_probe()
1387 chan->irq = ret; in stm32_dma_probe()
1389 ret = devm_request_irq(&pdev->dev, chan->irq, in stm32_dma_probe()
1393 dev_err(&pdev->dev, in stm32_dma_probe()
1400 ret = of_dma_controller_register(pdev->dev.of_node, in stm32_dma_probe()
1403 dev_err(&pdev->dev, in stm32_dma_probe()
1410 pm_runtime_set_active(&pdev->dev); in stm32_dma_probe()
1411 pm_runtime_enable(&pdev->dev); in stm32_dma_probe()
1412 pm_runtime_get_noresume(&pdev->dev); in stm32_dma_probe()
1413 pm_runtime_put(&pdev->dev); in stm32_dma_probe()
1415 dev_info(&pdev->dev, "STM32 DMA driver registered\n"); in stm32_dma_probe()
1422 clk_disable_unprepare(dmadev->clk); in stm32_dma_probe()
1432 clk_disable_unprepare(dmadev->clk); in stm32_dma_runtime_suspend()
1442 ret = clk_prepare_enable(dmadev->clk); in stm32_dma_runtime_resume()
1466 return -EBUSY; in stm32_dma_suspend()
1491 .name = "stm32-dma",