Lines Matching +full:pm +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0
32 u32 pm; member
42 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
43 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
54 * struct pch_gpio_reg_data - The register store data.
58 * @pm_reg: To store contents of PM register.
62 * (Only ML7223 Bus-n)
75 * struct pch_gpio - GPIO private data structure.
104 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_set()
105 reg_val = ioread32(&chip->reg->po); in pch_gpio_set()
111 iowrite32(reg_val, &chip->reg->po); in pch_gpio_set()
112 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_set()
119 return !!(ioread32(&chip->reg->pi) & BIT(nr)); in pch_gpio_get()
126 u32 pm; in pch_gpio_direction_output() local
130 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_direction_output()
132 reg_val = ioread32(&chip->reg->po); in pch_gpio_direction_output()
137 iowrite32(reg_val, &chip->reg->po); in pch_gpio_direction_output()
139 pm = ioread32(&chip->reg->pm); in pch_gpio_direction_output()
140 pm &= BIT(gpio_pins[chip->ioh]) - 1; in pch_gpio_direction_output()
141 pm |= BIT(nr); in pch_gpio_direction_output()
142 iowrite32(pm, &chip->reg->pm); in pch_gpio_direction_output()
144 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_direction_output()
152 u32 pm; in pch_gpio_direction_input() local
155 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_direction_input()
156 pm = ioread32(&chip->reg->pm); in pch_gpio_direction_input()
157 pm &= BIT(gpio_pins[chip->ioh]) - 1; in pch_gpio_direction_input()
158 pm &= ~BIT(nr); in pch_gpio_direction_input()
159 iowrite32(pm, &chip->reg->pm); in pch_gpio_direction_input()
160 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_direction_input()
170 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); in pch_gpio_save_reg_conf()
171 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); in pch_gpio_save_reg_conf()
172 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); in pch_gpio_save_reg_conf()
173 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); in pch_gpio_save_reg_conf()
174 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); in pch_gpio_save_reg_conf()
175 if (chip->ioh == INTEL_EG20T_PCH) in pch_gpio_save_reg_conf()
176 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); in pch_gpio_save_reg_conf()
177 if (chip->ioh == OKISEMI_ML7223n_IOH) in pch_gpio_save_reg_conf()
178 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel); in pch_gpio_save_reg_conf()
186 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien); in pch_gpio_restore_reg_conf()
187 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask); in pch_gpio_restore_reg_conf()
189 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); in pch_gpio_restore_reg_conf()
190 /* to store contents of PM register */ in pch_gpio_restore_reg_conf()
191 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); in pch_gpio_restore_reg_conf()
192 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); in pch_gpio_restore_reg_conf()
193 if (chip->ioh == INTEL_EG20T_PCH) in pch_gpio_restore_reg_conf()
194 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); in pch_gpio_restore_reg_conf()
195 if (chip->ioh == OKISEMI_ML7223n_IOH) in pch_gpio_restore_reg_conf()
196 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel); in pch_gpio_restore_reg_conf()
203 return chip->irq_base + offset; in pch_gpio_to_irq()
208 struct gpio_chip *gpio = &chip->gpio; in pch_gpio_setup()
210 gpio->label = dev_name(chip->dev); in pch_gpio_setup()
211 gpio->parent = chip->dev; in pch_gpio_setup()
212 gpio->owner = THIS_MODULE; in pch_gpio_setup()
213 gpio->direction_input = pch_gpio_direction_input; in pch_gpio_setup()
214 gpio->get = pch_gpio_get; in pch_gpio_setup()
215 gpio->direction_output = pch_gpio_direction_output; in pch_gpio_setup()
216 gpio->set = pch_gpio_set; in pch_gpio_setup()
217 gpio->base = -1; in pch_gpio_setup()
218 gpio->ngpio = gpio_pins[chip->ioh]; in pch_gpio_setup()
219 gpio->can_sleep = false; in pch_gpio_setup()
220 gpio->to_irq = pch_gpio_to_irq; in pch_gpio_setup()
226 struct pch_gpio *chip = gc->private; in pch_irq_type()
230 int ch, irq = d->irq; in pch_irq_type()
232 ch = irq - chip->irq_base; in pch_irq_type()
233 if (irq < chip->irq_base + 8) { in pch_irq_type()
234 im_reg = &chip->reg->im0; in pch_irq_type()
235 im_pos = ch - 0; in pch_irq_type()
237 im_reg = &chip->reg->im1; in pch_irq_type()
238 im_pos = ch - 8; in pch_irq_type()
240 dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos); in pch_irq_type()
262 spin_lock_irqsave(&chip->spinlock, flags); in pch_irq_type()
274 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_irq_type()
281 struct pch_gpio *chip = gc->private; in pch_irq_unmask()
283 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr); in pch_irq_unmask()
289 struct pch_gpio *chip = gc->private; in pch_irq_mask()
291 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask); in pch_irq_mask()
297 struct pch_gpio *chip = gc->private; in pch_irq_ack()
299 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr); in pch_irq_ack()
305 unsigned long reg_val = ioread32(&chip->reg->istatus); in pch_gpio_handler()
308 dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val); in pch_gpio_handler()
310 reg_val &= BIT(gpio_pins[chip->ioh]) - 1; in pch_gpio_handler()
312 for_each_set_bit(i, ®_val, gpio_pins[chip->ioh]) in pch_gpio_handler()
313 generic_handle_irq(chip->irq_base + i); in pch_gpio_handler()
326 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start, in pch_gpio_alloc_generic_chip()
327 chip->base, handle_simple_irq); in pch_gpio_alloc_generic_chip()
329 return -ENOMEM; in pch_gpio_alloc_generic_chip()
331 gc->private = chip; in pch_gpio_alloc_generic_chip()
332 ct = gc->chip_types; in pch_gpio_alloc_generic_chip()
334 ct->chip.irq_ack = pch_irq_ack; in pch_gpio_alloc_generic_chip()
335 ct->chip.irq_mask = pch_irq_mask; in pch_gpio_alloc_generic_chip()
336 ct->chip.irq_unmask = pch_irq_unmask; in pch_gpio_alloc_generic_chip()
337 ct->chip.irq_set_type = pch_irq_type; in pch_gpio_alloc_generic_chip()
339 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), in pch_gpio_alloc_generic_chip()
353 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); in pch_gpio_probe()
355 return -ENOMEM; in pch_gpio_probe()
357 chip->dev = &pdev->dev; in pch_gpio_probe()
360 dev_err(&pdev->dev, "pci_enable_device FAILED"); in pch_gpio_probe()
366 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret); in pch_gpio_probe()
370 chip->base = pcim_iomap_table(pdev)[1]; in pch_gpio_probe()
372 if (pdev->device == 0x8803) in pch_gpio_probe()
373 chip->ioh = INTEL_EG20T_PCH; in pch_gpio_probe()
374 else if (pdev->device == 0x8014) in pch_gpio_probe()
375 chip->ioh = OKISEMI_ML7223m_IOH; in pch_gpio_probe()
376 else if (pdev->device == 0x8043) in pch_gpio_probe()
377 chip->ioh = OKISEMI_ML7223n_IOH; in pch_gpio_probe()
379 chip->reg = chip->base; in pch_gpio_probe()
381 spin_lock_init(&chip->spinlock); in pch_gpio_probe()
384 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip); in pch_gpio_probe()
386 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n"); in pch_gpio_probe()
390 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, in pch_gpio_probe()
391 gpio_pins[chip->ioh], NUMA_NO_NODE); in pch_gpio_probe()
393 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n"); in pch_gpio_probe()
394 chip->irq_base = -1; in pch_gpio_probe()
397 chip->irq_base = irq_base; in pch_gpio_probe()
400 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask); in pch_gpio_probe()
401 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien); in pch_gpio_probe()
403 ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler, in pch_gpio_probe()
406 dev_err(&pdev->dev, "request_irq failed\n"); in pch_gpio_probe()
410 return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]); in pch_gpio_probe()
418 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_suspend()
420 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_suspend()
430 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_resume()
431 iowrite32(0x01, &chip->reg->reset); in pch_gpio_resume()
432 iowrite32(0x00, &chip->reg->reset); in pch_gpio_resume()
434 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_resume()
455 .pm = &pch_gpio_pm_ops,