Lines Matching +full:dphy +full:- +full:ref
1 // SPDX-License-Identifier: GPL-2.0+
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
85 * 2. Configure DSI Host and DPHY and enable DPHY
136 int ret = dsi->error; in nwl_dsi_clear_error()
138 dsi->error = 0; in nwl_dsi_clear_error()
146 if (dsi->error) in nwl_dsi_write()
149 ret = regmap_write(dsi->regmap, reg, val); in nwl_dsi_write()
151 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_write()
154 dsi->error = ret; in nwl_dsi_write()
163 if (dsi->error) in nwl_dsi_read()
166 ret = regmap_read(dsi->regmap, reg, &val); in nwl_dsi_read()
168 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n", in nwl_dsi_read()
170 dsi->error = ret; in nwl_dsi_read()
187 return -EINVAL; in nwl_dsi_get_dpi_pixel_format()
192 * ps2bc - Picoseconds to byte clock cycles
196 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in ps2bc()
198 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp, in ps2bc()
199 dsi->lanes * 8ULL * NSEC_PER_SEC); in ps2bc()
203 * ui2bc - UI time periods to byte clock cycles
207 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in ui2bc()
209 return DIV64_U64_ROUND_UP(ui * dsi->lanes, in ui2bc()
210 dsi->mode.clock * 1000 * bpp); in ui2bc()
214 * us2bc - micro seconds to lp clock cycles
224 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy; in nwl_dsi_config_host()
226 if (dsi->lanes < 1 || dsi->lanes > 4) in nwl_dsi_config_host()
227 return -EINVAL; in nwl_dsi_config_host()
229 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes); in nwl_dsi_config_host()
230 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1); in nwl_dsi_config_host()
232 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { in nwl_dsi_config_host()
241 cycles = ui2bc(dsi, cfg->clk_pre); in nwl_dsi_config_host()
242 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles); in nwl_dsi_config_host()
244 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero); in nwl_dsi_config_host()
245 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles); in nwl_dsi_config_host()
246 cycles += ui2bc(dsi, cfg->clk_pre); in nwl_dsi_config_host()
247 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles); in nwl_dsi_config_host()
249 cycles = ps2bc(dsi, cfg->hs_exit); in nwl_dsi_config_host()
250 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles); in nwl_dsi_config_host()
258 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup); in nwl_dsi_config_host()
259 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles); in nwl_dsi_config_host()
273 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay; in nwl_dsi_config_dpi()
274 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start; in nwl_dsi_config_dpi()
275 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end; in nwl_dsi_config_dpi()
277 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay; in nwl_dsi_config_dpi()
278 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start; in nwl_dsi_config_dpi()
279 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end; in nwl_dsi_config_dpi()
281 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch); in nwl_dsi_config_dpi()
282 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch); in nwl_dsi_config_dpi()
283 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len); in nwl_dsi_config_dpi()
284 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay); in nwl_dsi_config_dpi()
285 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch); in nwl_dsi_config_dpi()
286 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch); in nwl_dsi_config_dpi()
287 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len); in nwl_dsi_config_dpi()
288 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay); in nwl_dsi_config_dpi()
289 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock); in nwl_dsi_config_dpi()
291 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format); in nwl_dsi_config_dpi()
293 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n", in nwl_dsi_config_dpi()
294 dsi->format); in nwl_dsi_config_dpi()
297 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format); in nwl_dsi_config_dpi()
310 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && in nwl_dsi_config_dpi()
311 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE); in nwl_dsi_config_dpi()
317 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ? in nwl_dsi_config_dpi()
322 dsi->mode.hdisplay); in nwl_dsi_config_dpi()
334 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay); in nwl_dsi_config_dpi()
335 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1); in nwl_dsi_config_dpi()
363 struct device *dev = dsi->dev; in nwl_dsi_host_attach()
365 DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes, in nwl_dsi_host_attach()
366 device->format, device->mode_flags); in nwl_dsi_host_attach()
368 if (device->lanes < 1 || device->lanes > 4) in nwl_dsi_host_attach()
369 return -EINVAL; in nwl_dsi_host_attach()
371 dsi->lanes = device->lanes; in nwl_dsi_host_attach()
372 dsi->format = device->format; in nwl_dsi_host_attach()
373 dsi->dsi_mode_flags = device->mode_flags; in nwl_dsi_host_attach()
380 struct device *dev = dsi->dev; in nwl_dsi_read_packet()
381 struct nwl_dsi_transfer *xfer = dsi->xfer; in nwl_dsi_read_packet()
383 u8 *payload = xfer->msg->rx_buf; in nwl_dsi_read_packet()
389 xfer->status = 0; in nwl_dsi_read_packet()
391 if (xfer->rx_word_count == 0) { in nwl_dsi_read_packet()
398 xfer->status = err; in nwl_dsi_read_packet()
403 if (channel != xfer->msg->channel) { in nwl_dsi_read_packet()
406 xfer->cmd, channel, xfer->msg->channel); in nwl_dsi_read_packet()
407 xfer->status = -EINVAL; in nwl_dsi_read_packet()
414 if (xfer->msg->rx_len > 1) { in nwl_dsi_read_packet()
417 ++xfer->rx_len; in nwl_dsi_read_packet()
422 if (xfer->msg->rx_len > 0) { in nwl_dsi_read_packet()
425 ++xfer->rx_len; in nwl_dsi_read_packet()
427 xfer->status = xfer->rx_len; in nwl_dsi_read_packet()
432 xfer->cmd, word_count); in nwl_dsi_read_packet()
433 xfer->status = -EPROTO; in nwl_dsi_read_packet()
437 if (word_count > xfer->msg->rx_len) { in nwl_dsi_read_packet()
440 xfer->cmd, xfer->msg->rx_len, word_count); in nwl_dsi_read_packet()
441 xfer->status = -EINVAL; in nwl_dsi_read_packet()
445 xfer->rx_word_count = word_count; in nwl_dsi_read_packet()
448 word_count = xfer->rx_word_count; in nwl_dsi_read_packet()
463 xfer->rx_len += 4; in nwl_dsi_read_packet()
464 word_count -= 4; in nwl_dsi_read_packet()
472 ++xfer->rx_len; in nwl_dsi_read_packet()
476 ++xfer->rx_len; in nwl_dsi_read_packet()
480 ++xfer->rx_len; in nwl_dsi_read_packet()
485 xfer->status = xfer->rx_len; in nwl_dsi_read_packet()
488 xfer->status = err; in nwl_dsi_read_packet()
495 struct nwl_dsi_transfer *xfer = dsi->xfer; in nwl_dsi_finish_transmission()
501 if (xfer->direction == DSI_PACKET_SEND && in nwl_dsi_finish_transmission()
503 xfer->status = xfer->tx_len; in nwl_dsi_finish_transmission()
512 complete(&xfer->completed); in nwl_dsi_finish_transmission()
517 struct nwl_dsi_transfer *xfer = dsi->xfer; in nwl_dsi_begin_transmission()
518 struct mipi_dsi_packet *pkt = &xfer->packet; in nwl_dsi_begin_transmission()
527 length = pkt->payload_length; in nwl_dsi_begin_transmission()
528 payload = pkt->payload; in nwl_dsi_begin_transmission()
535 length -= 4; in nwl_dsi_begin_transmission()
552 xfer->tx_len = pkt->payload_length; in nwl_dsi_begin_transmission()
560 word_count = pkt->header[1] | (pkt->header[2] << 8); in nwl_dsi_begin_transmission()
561 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) { in nwl_dsi_begin_transmission()
562 DRM_DEV_DEBUG_DRIVER(dsi->dev, in nwl_dsi_begin_transmission()
564 xfer->cmd); in nwl_dsi_begin_transmission()
567 hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1; in nwl_dsi_begin_transmission()
569 val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) | in nwl_dsi_begin_transmission()
570 NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) | in nwl_dsi_begin_transmission()
571 NWL_DSI_BTA_TX(xfer->need_bta); in nwl_dsi_begin_transmission()
586 dsi->xfer = &xfer; in nwl_dsi_host_transfer()
589 dsi->xfer = NULL; in nwl_dsi_host_transfer()
593 if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM || in nwl_dsi_host_transfer()
594 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM || in nwl_dsi_host_transfer()
595 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM || in nwl_dsi_host_transfer()
596 msg->type & MIPI_DSI_DCS_READ) && in nwl_dsi_host_transfer()
597 msg->rx_len > 0 && msg->rx_buf) in nwl_dsi_host_transfer()
603 xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0; in nwl_dsi_host_transfer()
605 xfer.status = -ETIMEDOUT; in nwl_dsi_host_transfer()
609 if (msg->tx_len > 0) in nwl_dsi_host_transfer()
610 xfer.cmd = ((u8 *)(msg->tx_buf))[0]; in nwl_dsi_host_transfer()
613 ret = clk_prepare_enable(dsi->rx_esc_clk); in nwl_dsi_host_transfer()
615 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n", in nwl_dsi_host_transfer()
619 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n", in nwl_dsi_host_transfer()
620 clk_get_rate(dsi->rx_esc_clk)); in nwl_dsi_host_transfer()
627 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n", in nwl_dsi_host_transfer()
629 ret = -ETIMEDOUT; in nwl_dsi_host_transfer()
634 clk_disable_unprepare(dsi->rx_esc_clk); in nwl_dsi_host_transfer()
652 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n"); in nwl_dsi_irq_handler()
655 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n"); in nwl_dsi_irq_handler()
667 struct device *dev = dsi->dev; in nwl_dsi_enable()
668 union phy_configure_opts *phy_cfg = &dsi->phy_cfg; in nwl_dsi_enable()
671 if (!dsi->lanes) { in nwl_dsi_enable()
672 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes); in nwl_dsi_enable()
673 return -EINVAL; in nwl_dsi_enable()
676 ret = phy_init(dsi->phy); in nwl_dsi_enable()
682 ret = phy_configure(dsi->phy, phy_cfg); in nwl_dsi_enable()
688 ret = clk_prepare_enable(dsi->tx_esc_clk); in nwl_dsi_enable()
690 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n", in nwl_dsi_enable()
694 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n", in nwl_dsi_enable()
695 clk_get_rate(dsi->tx_esc_clk)); in nwl_dsi_enable()
709 ret = phy_power_on(dsi->phy); in nwl_dsi_enable()
711 DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret); in nwl_dsi_enable()
722 phy_power_off(dsi->phy); in nwl_dsi_enable()
724 clk_disable_unprepare(dsi->tx_esc_clk); in nwl_dsi_enable()
726 phy_exit(dsi->phy); in nwl_dsi_enable()
733 struct device *dev = dsi->dev; in nwl_dsi_disable()
737 phy_power_off(dsi->phy); in nwl_dsi_disable()
738 phy_exit(dsi->phy); in nwl_dsi_disable()
741 clk_disable_unprepare(dsi->tx_esc_clk); in nwl_dsi_disable()
755 ret = reset_control_assert(dsi->rst_dpi); in nwl_dsi_bridge_atomic_disable()
757 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret); in nwl_dsi_bridge_atomic_disable()
760 ret = reset_control_assert(dsi->rst_byte); in nwl_dsi_bridge_atomic_disable()
762 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret); in nwl_dsi_bridge_atomic_disable()
765 ret = reset_control_assert(dsi->rst_esc); in nwl_dsi_bridge_atomic_disable()
767 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret); in nwl_dsi_bridge_atomic_disable()
770 ret = reset_control_assert(dsi->rst_pclk); in nwl_dsi_bridge_atomic_disable()
772 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret); in nwl_dsi_bridge_atomic_disable()
776 clk_disable_unprepare(dsi->core_clk); in nwl_dsi_bridge_atomic_disable()
777 clk_disable_unprepare(dsi->lcdif_clk); in nwl_dsi_bridge_atomic_disable()
779 pm_runtime_put(dsi->dev); in nwl_dsi_bridge_atomic_disable()
789 if (dsi->lanes < 1 || dsi->lanes > 4) in nwl_dsi_get_dphy_params()
790 return -EINVAL; in nwl_dsi_get_dphy_params()
793 * So far the DPHY spec minimal timings work for both mixel in nwl_dsi_get_dphy_params()
794 * dphy and nwl dsi host in nwl_dsi_get_dphy_params()
796 ret = phy_mipi_dphy_get_default_config(mode->clock * 1000, in nwl_dsi_get_dphy_params()
797 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes, in nwl_dsi_get_dphy_params()
798 &phy_opts->mipi_dphy); in nwl_dsi_get_dphy_params()
802 rate = clk_get_rate(dsi->tx_esc_clk); in nwl_dsi_get_dphy_params()
803 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate); in nwl_dsi_get_dphy_params()
804 phy_opts->mipi_dphy.lp_clk_rate = rate; in nwl_dsi_get_dphy_params()
815 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in nwl_dsi_bridge_mode_valid()
817 if (mode->clock * bpp > 15000000 * dsi->lanes) in nwl_dsi_bridge_mode_valid()
820 if (mode->clock * bpp < 80000 * dsi->lanes) in nwl_dsi_bridge_mode_valid()
831 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; in nwl_dsi_bridge_atomic_check()
834 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); in nwl_dsi_bridge_atomic_check()
835 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); in nwl_dsi_bridge_atomic_check()
837 /* Do a full modeset if crtc_state->active is changed to be true. */ in nwl_dsi_bridge_atomic_check()
838 if (crtc_state->active_changed && crtc_state->active) in nwl_dsi_bridge_atomic_check()
839 crtc_state->mode_changed = true; in nwl_dsi_bridge_atomic_check()
850 struct device *dev = dsi->dev; in nwl_dsi_bridge_mode_set()
860 * If hs clock is unchanged, we're all good - all parameters are in nwl_dsi_bridge_mode_set()
863 if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate) in nwl_dsi_bridge_mode_set()
866 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk); in nwl_dsi_bridge_mode_set()
867 DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate); in nwl_dsi_bridge_mode_set()
869 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg)); in nwl_dsi_bridge_mode_set()
871 memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode)); in nwl_dsi_bridge_mode_set()
882 pm_runtime_get_sync(dsi->dev); in nwl_dsi_bridge_atomic_pre_enable()
884 if (clk_prepare_enable(dsi->lcdif_clk) < 0) in nwl_dsi_bridge_atomic_pre_enable()
886 if (clk_prepare_enable(dsi->core_clk) < 0) in nwl_dsi_bridge_atomic_pre_enable()
889 /* Step 1 from DSI reset-out instructions */ in nwl_dsi_bridge_atomic_pre_enable()
890 ret = reset_control_deassert(dsi->rst_pclk); in nwl_dsi_bridge_atomic_pre_enable()
892 DRM_DEV_ERROR(dsi->dev, "Failed to deassert PCLK: %d\n", ret); in nwl_dsi_bridge_atomic_pre_enable()
896 /* Step 2 from DSI reset-out instructions */ in nwl_dsi_bridge_atomic_pre_enable()
899 /* Step 3 from DSI reset-out instructions */ in nwl_dsi_bridge_atomic_pre_enable()
900 ret = reset_control_deassert(dsi->rst_esc); in nwl_dsi_bridge_atomic_pre_enable()
902 DRM_DEV_ERROR(dsi->dev, "Failed to deassert ESC: %d\n", ret); in nwl_dsi_bridge_atomic_pre_enable()
905 ret = reset_control_deassert(dsi->rst_byte); in nwl_dsi_bridge_atomic_pre_enable()
907 DRM_DEV_ERROR(dsi->dev, "Failed to deassert BYTE: %d\n", ret); in nwl_dsi_bridge_atomic_pre_enable()
919 /* Step 5 from DSI reset-out instructions */ in nwl_dsi_bridge_atomic_enable()
920 ret = reset_control_deassert(dsi->rst_dpi); in nwl_dsi_bridge_atomic_enable()
922 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret); in nwl_dsi_bridge_atomic_enable()
933 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel, in nwl_dsi_bridge_attach()
943 dsi->panel_bridge = panel_bridge; in nwl_dsi_bridge_attach()
945 if (!dsi->panel_bridge) in nwl_dsi_bridge_attach()
946 return -EPROBE_DEFER; in nwl_dsi_bridge_attach()
948 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge, in nwl_dsi_bridge_attach()
955 drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0); in nwl_dsi_bridge_detach()
974 struct platform_device *pdev = to_platform_device(dsi->dev); in nwl_dsi_parse_dt()
979 dsi->phy = devm_phy_get(dsi->dev, "dphy"); in nwl_dsi_parse_dt()
980 if (IS_ERR(dsi->phy)) { in nwl_dsi_parse_dt()
981 ret = PTR_ERR(dsi->phy); in nwl_dsi_parse_dt()
982 if (ret != -EPROBE_DEFER) in nwl_dsi_parse_dt()
983 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret); in nwl_dsi_parse_dt()
987 clk = devm_clk_get(dsi->dev, "lcdif"); in nwl_dsi_parse_dt()
990 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n", in nwl_dsi_parse_dt()
994 dsi->lcdif_clk = clk; in nwl_dsi_parse_dt()
996 clk = devm_clk_get(dsi->dev, "core"); in nwl_dsi_parse_dt()
999 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n", in nwl_dsi_parse_dt()
1003 dsi->core_clk = clk; in nwl_dsi_parse_dt()
1005 clk = devm_clk_get(dsi->dev, "phy_ref"); in nwl_dsi_parse_dt()
1008 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n", in nwl_dsi_parse_dt()
1012 dsi->phy_ref_clk = clk; in nwl_dsi_parse_dt()
1014 clk = devm_clk_get(dsi->dev, "rx_esc"); in nwl_dsi_parse_dt()
1017 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n", in nwl_dsi_parse_dt()
1021 dsi->rx_esc_clk = clk; in nwl_dsi_parse_dt()
1023 clk = devm_clk_get(dsi->dev, "tx_esc"); in nwl_dsi_parse_dt()
1026 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n", in nwl_dsi_parse_dt()
1030 dsi->tx_esc_clk = clk; in nwl_dsi_parse_dt()
1032 dsi->mux = devm_mux_control_get(dsi->dev, NULL); in nwl_dsi_parse_dt()
1033 if (IS_ERR(dsi->mux)) { in nwl_dsi_parse_dt()
1034 ret = PTR_ERR(dsi->mux); in nwl_dsi_parse_dt()
1035 if (ret != -EPROBE_DEFER) in nwl_dsi_parse_dt()
1036 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret); in nwl_dsi_parse_dt()
1044 dsi->regmap = in nwl_dsi_parse_dt()
1045 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config); in nwl_dsi_parse_dt()
1046 if (IS_ERR(dsi->regmap)) { in nwl_dsi_parse_dt()
1047 ret = PTR_ERR(dsi->regmap); in nwl_dsi_parse_dt()
1048 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n", in nwl_dsi_parse_dt()
1053 dsi->irq = platform_get_irq(pdev, 0); in nwl_dsi_parse_dt()
1054 if (dsi->irq < 0) { in nwl_dsi_parse_dt()
1055 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n", in nwl_dsi_parse_dt()
1056 dsi->irq); in nwl_dsi_parse_dt()
1057 return dsi->irq; in nwl_dsi_parse_dt()
1060 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk"); in nwl_dsi_parse_dt()
1061 if (IS_ERR(dsi->rst_pclk)) { in nwl_dsi_parse_dt()
1062 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n", in nwl_dsi_parse_dt()
1063 PTR_ERR(dsi->rst_pclk)); in nwl_dsi_parse_dt()
1064 return PTR_ERR(dsi->rst_pclk); in nwl_dsi_parse_dt()
1066 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte"); in nwl_dsi_parse_dt()
1067 if (IS_ERR(dsi->rst_byte)) { in nwl_dsi_parse_dt()
1068 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n", in nwl_dsi_parse_dt()
1069 PTR_ERR(dsi->rst_byte)); in nwl_dsi_parse_dt()
1070 return PTR_ERR(dsi->rst_byte); in nwl_dsi_parse_dt()
1072 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc"); in nwl_dsi_parse_dt()
1073 if (IS_ERR(dsi->rst_esc)) { in nwl_dsi_parse_dt()
1074 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n", in nwl_dsi_parse_dt()
1075 PTR_ERR(dsi->rst_esc)); in nwl_dsi_parse_dt()
1076 return PTR_ERR(dsi->rst_esc); in nwl_dsi_parse_dt()
1078 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi"); in nwl_dsi_parse_dt()
1079 if (IS_ERR(dsi->rst_dpi)) { in nwl_dsi_parse_dt()
1080 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n", in nwl_dsi_parse_dt()
1081 PTR_ERR(dsi->rst_dpi)); in nwl_dsi_parse_dt()
1082 return PTR_ERR(dsi->rst_dpi); in nwl_dsi_parse_dt()
1093 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, in nwl_dsi_select_input()
1098 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, in nwl_dsi_select_input()
1101 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_select_input()
1103 return -EINVAL; in nwl_dsi_select_input()
1107 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n", in nwl_dsi_select_input()
1109 ret = mux_control_try_select(dsi->mux, use_dcss); in nwl_dsi_select_input()
1111 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret); in nwl_dsi_select_input()
1121 ret = mux_control_deselect(dsi->mux); in nwl_dsi_deselect_input()
1123 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret); in nwl_dsi_deselect_input()
1133 { .compatible = "fsl,imx8mq-nwl-dsi", },
1146 struct device *dev = &pdev->dev; in nwl_dsi_probe()
1153 return -ENOMEM; in nwl_dsi_probe()
1155 dsi->dev = dev; in nwl_dsi_probe()
1161 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0, in nwl_dsi_probe()
1164 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq, in nwl_dsi_probe()
1169 dsi->dsi_host.ops = &nwl_dsi_host_ops; in nwl_dsi_probe()
1170 dsi->dsi_host.dev = dev; in nwl_dsi_probe()
1171 ret = mipi_dsi_host_register(&dsi->dsi_host); in nwl_dsi_probe()
1179 dsi->quirks = (uintptr_t)attr->data; in nwl_dsi_probe()
1181 dsi->bridge.driver_private = dsi; in nwl_dsi_probe()
1182 dsi->bridge.funcs = &nwl_dsi_bridge_funcs; in nwl_dsi_probe()
1183 dsi->bridge.of_node = dev->of_node; in nwl_dsi_probe()
1184 dsi->bridge.timings = &nwl_dsi_timings; in nwl_dsi_probe()
1191 mipi_dsi_host_unregister(&dsi->dsi_host); in nwl_dsi_probe()
1195 drm_bridge_add(&dsi->bridge); in nwl_dsi_probe()
1204 mipi_dsi_host_unregister(&dsi->dsi_host); in nwl_dsi_remove()
1205 drm_bridge_remove(&dsi->bridge); in nwl_dsi_remove()
1206 pm_runtime_disable(&pdev->dev); in nwl_dsi_remove()
1223 MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver");