Lines Matching full:tcon
83 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_channel_set_status() argument
90 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon_channel_set_status()
91 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_channel_set_status()
94 clk = tcon->dclk; in sun4i_tcon_channel_set_status()
97 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon_channel_set_status()
98 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_channel_set_status()
101 clk = tcon->sclk1; in sun4i_tcon_channel_set_status()
117 static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, in sun4i_tcon_setup_lvds_phy() argument
120 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
129 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
133 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
136 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
141 static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, in sun6i_tcon_setup_lvds_phy() argument
146 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
153 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
158 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
167 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
172 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, in sun4i_tcon_lvds_set_status() argument
177 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
180 if (tcon->quirks->setup_lvds_phy) in sun4i_tcon_lvds_set_status()
181 tcon->quirks->setup_lvds_phy(tcon, encoder); in sun4i_tcon_lvds_set_status()
183 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
188 void sun4i_tcon_set_status(struct sun4i_tcon *tcon, in sun4i_tcon_set_status() argument
213 sun4i_tcon_lvds_set_status(tcon, encoder, false); in sun4i_tcon_set_status()
215 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon_set_status()
220 sun4i_tcon_lvds_set_status(tcon, encoder, true); in sun4i_tcon_set_status()
222 sun4i_tcon_channel_set_status(tcon, channel, enabled); in sun4i_tcon_set_status()
225 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) in sun4i_tcon_enable_vblank() argument
238 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); in sun4i_tcon_enable_vblank()
243 * This function is a helper for TCON output muxing. The TCON output
244 * muxing control register in earlier SoCs (without the TCON TOP block)
251 struct sun4i_tcon *tcon; in sun4i_get_tcon0() local
253 list_for_each_entry(tcon, &drv->tcon_list, list) in sun4i_get_tcon0()
254 if (tcon->id == 0) in sun4i_get_tcon0()
255 return tcon; in sun4i_get_tcon0()
263 static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_set_mux() argument
268 if (tcon->quirks->set_mux) in sun4i_tcon_set_mux()
269 ret = tcon->quirks->set_mux(tcon, encoder); in sun4i_tcon_set_mux()
288 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay); in sun4i_tcon_get_clk_delay()
293 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_common() argument
297 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_common()
300 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_common()
305 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_dithering() argument
321 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
322 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
323 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
324 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
325 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
326 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
327 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); in sun4i_tcon0_mode_set_dithering()
328 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); in sun4i_tcon0_mode_set_dithering()
329 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); in sun4i_tcon0_mode_set_dithering()
330 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); in sun4i_tcon0_mode_set_dithering()
354 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); in sun4i_tcon0_mode_set_dithering()
357 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_cpu() argument
369 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
370 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
372 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_cpu()
375 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); in sun4i_tcon0_mode_set_cpu()
377 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_cpu()
381 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, in sun4i_tcon0_mode_set_cpu()
384 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, in sun4i_tcon0_mode_set_cpu()
396 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); in sun4i_tcon0_mode_set_cpu()
401 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, in sun4i_tcon0_mode_set_cpu()
405 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, in sun4i_tcon0_mode_set_cpu()
411 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, in sun4i_tcon0_mode_set_cpu()
419 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, in sun4i_tcon0_mode_set_cpu()
424 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, in sun4i_tcon0_mode_set_cpu()
428 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_lvds() argument
436 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_lvds()
438 tcon->dclk_min_div = 7; in sun4i_tcon0_mode_set_lvds()
439 tcon->dclk_max_div = 7; in sun4i_tcon0_mode_set_lvds()
440 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_lvds()
443 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); in sun4i_tcon0_mode_set_lvds()
447 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_lvds()
460 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_lvds()
473 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_lvds()
483 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); in sun4i_tcon0_mode_set_lvds()
492 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon0_mode_set_lvds()
495 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_lvds()
500 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); in sun4i_tcon0_mode_set_lvds()
503 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_rgb() argument
513 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_rgb()
515 tcon->dclk_min_div = tcon->quirks->dclk_min_div; in sun4i_tcon0_mode_set_rgb()
516 tcon->dclk_max_div = 127; in sun4i_tcon0_mode_set_rgb()
517 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_rgb()
520 sun4i_tcon0_mode_set_dithering(tcon, connector); in sun4i_tcon0_mode_set_rgb()
524 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_rgb()
537 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_rgb()
550 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_rgb()
558 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, in sun4i_tcon0_mode_set_rgb()
575 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, in sun4i_tcon0_mode_set_rgb()
583 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_rgb()
588 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); in sun4i_tcon0_mode_set_rgb()
591 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, in sun4i_tcon1_mode_set() argument
598 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon1_mode_set()
601 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); in sun4i_tcon1_mode_set()
605 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
614 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
619 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, in sun4i_tcon1_mode_set()
624 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, in sun4i_tcon1_mode_set()
629 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, in sun4i_tcon1_mode_set()
637 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, in sun4i_tcon1_mode_set()
663 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, in sun4i_tcon1_mode_set()
671 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, in sun4i_tcon1_mode_set()
676 if (tcon->quirks->polarity_in_ch0) { in sun4i_tcon1_mode_set()
685 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon1_mode_set()
696 regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val); in sun4i_tcon1_mode_set()
700 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon1_mode_set()
705 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, in sun4i_tcon_mode_set() argument
712 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); in sun4i_tcon_mode_set()
715 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); in sun4i_tcon_mode_set()
718 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode); in sun4i_tcon_mode_set()
719 sun4i_tcon_set_mux(tcon, 0, encoder); in sun4i_tcon_mode_set()
723 sun4i_tcon1_mode_set(tcon, mode); in sun4i_tcon_mode_set()
724 sun4i_tcon_set_mux(tcon, 1, encoder); in sun4i_tcon_mode_set()
748 struct sun4i_tcon *tcon = private; in sun4i_tcon_handler() local
749 struct drm_device *drm = tcon->drm; in sun4i_tcon_handler()
750 struct sun4i_crtc *scrtc = tcon->crtc; in sun4i_tcon_handler()
754 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); in sun4i_tcon_handler()
765 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, in sun4i_tcon_handler()
778 struct sun4i_tcon *tcon) in sun4i_tcon_init_clocks() argument
780 tcon->clk = devm_clk_get(dev, "ahb"); in sun4i_tcon_init_clocks()
781 if (IS_ERR(tcon->clk)) { in sun4i_tcon_init_clocks()
782 dev_err(dev, "Couldn't get the TCON bus clock\n"); in sun4i_tcon_init_clocks()
783 return PTR_ERR(tcon->clk); in sun4i_tcon_init_clocks()
785 clk_prepare_enable(tcon->clk); in sun4i_tcon_init_clocks()
787 if (tcon->quirks->has_channel_0) { in sun4i_tcon_init_clocks()
788 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); in sun4i_tcon_init_clocks()
789 if (IS_ERR(tcon->sclk0)) { in sun4i_tcon_init_clocks()
790 dev_err(dev, "Couldn't get the TCON channel 0 clock\n"); in sun4i_tcon_init_clocks()
791 return PTR_ERR(tcon->sclk0); in sun4i_tcon_init_clocks()
794 clk_prepare_enable(tcon->sclk0); in sun4i_tcon_init_clocks()
796 if (tcon->quirks->has_channel_1) { in sun4i_tcon_init_clocks()
797 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); in sun4i_tcon_init_clocks()
798 if (IS_ERR(tcon->sclk1)) { in sun4i_tcon_init_clocks()
799 dev_err(dev, "Couldn't get the TCON channel 1 clock\n"); in sun4i_tcon_init_clocks()
800 return PTR_ERR(tcon->sclk1); in sun4i_tcon_init_clocks()
807 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon) in sun4i_tcon_free_clocks() argument
809 clk_disable_unprepare(tcon->sclk0); in sun4i_tcon_free_clocks()
810 clk_disable_unprepare(tcon->clk); in sun4i_tcon_free_clocks()
814 struct sun4i_tcon *tcon) in sun4i_tcon_init_irq() argument
824 dev_name(dev), tcon); in sun4i_tcon_init_irq()
841 struct sun4i_tcon *tcon) in sun4i_tcon_init_regmap() argument
852 tcon->regs = devm_regmap_init_mmio(dev, regs, in sun4i_tcon_init_regmap()
854 if (IS_ERR(tcon->regs)) { in sun4i_tcon_init_regmap()
855 dev_err(dev, "Couldn't create the TCON regmap\n"); in sun4i_tcon_init_regmap()
856 return PTR_ERR(tcon->regs); in sun4i_tcon_init_regmap()
859 /* Make sure the TCON is disabled and all IRQs are off */ in sun4i_tcon_init_regmap()
860 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); in sun4i_tcon_init_regmap()
861 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); in sun4i_tcon_init_regmap()
862 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); in sun4i_tcon_init_regmap()
865 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
866 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
873 * the TCON is always tied to just one backend. Hence we can traverse
874 * the of_graph upwards to find the backend our tcon is connected to,
879 * registered and binded before the TCON, we can just go through the
900 * This only works if there is only one path from the TCON in sun4i_tcon_find_engine_traverse()
928 * more than one input and one output (TCON TOP) exits, correct in sun4i_tcon_find_engine_traverse()
953 * connection between components, up to and including the TCON, of
986 * Once we know the TCON's id, we can look through the list of
1023 * Because TCON is added to the list at the end of the probe in sun4i_tcon_get_index()
1024 * (after this function is called), index of the current TCON in sun4i_tcon_get_index()
1025 * will be same as current TCON list size. in sun4i_tcon_get_index()
1035 * we assumed the TCON was always tied to just one backend. However
1036 * this proved not to be the case. On the A31, the TCON can select
1038 * the backend can choose which TCON to output to.
1041 * connection between components, up to and including the TCON, of
1047 * However the connections between the backend and TCON were assumed
1050 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
1053 * This function first checks if the TCON node has 2 input endpoints.
1058 * have endpoint connections between the backend and TCON across
1078 * connections between the backend and TCON? in sun4i_tcon_find_engine()
1087 * contains TCON TOP, chances are that there are either more in sun4i_tcon_find_engine()
1089 * (H6). In that case it's easier just use TCON index in list in sun4i_tcon_find_engine()
1092 * TCON TOP, remaining 2 TCONs can't be connected to anything in sun4i_tcon_find_engine()
1119 struct sun4i_tcon *tcon; in sun4i_tcon_bind() local
1130 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL); in sun4i_tcon_bind()
1131 if (!tcon) in sun4i_tcon_bind()
1133 dev_set_drvdata(dev, tcon); in sun4i_tcon_bind()
1134 tcon->drm = drm; in sun4i_tcon_bind()
1135 tcon->dev = dev; in sun4i_tcon_bind()
1136 tcon->id = engine->id; in sun4i_tcon_bind()
1137 tcon->quirks = of_device_get_match_data(dev); in sun4i_tcon_bind()
1139 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); in sun4i_tcon_bind()
1140 if (IS_ERR(tcon->lcd_rst)) { in sun4i_tcon_bind()
1142 return PTR_ERR(tcon->lcd_rst); in sun4i_tcon_bind()
1145 if (tcon->quirks->needs_edp_reset) { in sun4i_tcon_bind()
1159 /* Make sure our TCON is reset */ in sun4i_tcon_bind()
1160 ret = reset_control_reset(tcon->lcd_rst); in sun4i_tcon_bind()
1166 if (tcon->quirks->supports_lvds) { in sun4i_tcon_bind()
1174 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); in sun4i_tcon_bind()
1175 if (IS_ERR(tcon->lvds_rst)) { in sun4i_tcon_bind()
1177 return PTR_ERR(tcon->lvds_rst); in sun4i_tcon_bind()
1178 } else if (tcon->lvds_rst) { in sun4i_tcon_bind()
1180 reset_control_reset(tcon->lvds_rst); in sun4i_tcon_bind()
1192 if (tcon->quirks->has_lvds_alt) { in sun4i_tcon_bind()
1193 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); in sun4i_tcon_bind()
1194 if (IS_ERR(tcon->lvds_pll)) { in sun4i_tcon_bind()
1195 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { in sun4i_tcon_bind()
1199 return PTR_ERR(tcon->lvds_pll); in sun4i_tcon_bind()
1207 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { in sun4i_tcon_bind()
1218 ret = sun4i_tcon_init_clocks(dev, tcon); in sun4i_tcon_bind()
1220 dev_err(dev, "Couldn't init our TCON clocks\n"); in sun4i_tcon_bind()
1224 ret = sun4i_tcon_init_regmap(dev, tcon); in sun4i_tcon_bind()
1226 dev_err(dev, "Couldn't init our TCON regmap\n"); in sun4i_tcon_bind()
1230 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1231 ret = sun4i_dclk_create(dev, tcon); in sun4i_tcon_bind()
1233 dev_err(dev, "Couldn't create our TCON dot clock\n"); in sun4i_tcon_bind()
1238 ret = sun4i_tcon_init_irq(dev, tcon); in sun4i_tcon_bind()
1240 dev_err(dev, "Couldn't init our TCON interrupts\n"); in sun4i_tcon_bind()
1244 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); in sun4i_tcon_bind()
1245 if (IS_ERR(tcon->crtc)) { in sun4i_tcon_bind()
1247 ret = PTR_ERR(tcon->crtc); in sun4i_tcon_bind()
1251 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1253 * If we have an LVDS panel connected to the TCON, we should in sun4i_tcon_bind()
1260 ret = sun4i_lvds_init(drm, tcon); in sun4i_tcon_bind()
1264 ret = sun4i_rgb_init(drm, tcon); in sun4i_tcon_bind()
1271 if (tcon->quirks->needs_de_be_mux) { in sun4i_tcon_bind()
1277 * the CRTC is tied to the TCON, while the layers are in sun4i_tcon_bind()
1282 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_bind()
1284 tcon->id); in sun4i_tcon_bind()
1285 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_bind()
1287 tcon->id); in sun4i_tcon_bind()
1290 list_add_tail(&tcon->list, &drv->tcon_list); in sun4i_tcon_bind()
1295 if (tcon->quirks->has_channel_0) in sun4i_tcon_bind()
1296 sun4i_dclk_free(tcon); in sun4i_tcon_bind()
1298 sun4i_tcon_free_clocks(tcon); in sun4i_tcon_bind()
1300 reset_control_assert(tcon->lcd_rst); in sun4i_tcon_bind()
1307 struct sun4i_tcon *tcon = dev_get_drvdata(dev); in sun4i_tcon_unbind() local
1309 list_del(&tcon->list); in sun4i_tcon_unbind()
1310 if (tcon->quirks->has_channel_0) in sun4i_tcon_unbind()
1311 sun4i_dclk_free(tcon); in sun4i_tcon_unbind()
1312 sun4i_tcon_free_clocks(tcon); in sun4i_tcon_unbind()
1347 /* platform specific TCON muxing callbacks */
1348 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon, in sun4i_a10_tcon_set_mux() argument
1367 0x3 << shift, tcon->id << shift); in sun4i_a10_tcon_set_mux()
1372 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon, in sun5i_a13_tcon_set_mux() argument
1385 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); in sun5i_a13_tcon_set_mux()
1388 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, in sun6i_tcon_set_mux() argument
1408 0x3 << shift, tcon->id << shift); in sun6i_tcon_set_mux()
1413 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon, in sun8i_r40_tcon_tv_set_mux() argument
1420 /* find TCON TOP platform device and TCON id */ in sun8i_r40_tcon_tv_set_mux()
1422 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); in sun8i_r40_tcon_tv_set_mux()
1429 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); in sun8i_r40_tcon_tv_set_mux()
1448 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); in sun8i_r40_tcon_tv_set_mux()
1547 /* sun4i_drv uses this list to check if a device node is a TCON */
1549 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1550 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1551 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1552 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1553 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1556 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
1557 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1558 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1559 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1560 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1561 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1562 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1563 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1573 .name = "sun4i-tcon",