1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
58 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_get_irqchip_state()
68 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_set_irqchip_state()
76 	int pin_out = d->hwirq;  in pdc_enable_intr()
78 	u32 enable;  in pdc_enable_intr()  local
84 	enable = pdc_reg_read(IRQ_ENABLE_BANK, index);  in pdc_enable_intr()
85 	enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);  in pdc_enable_intr()
86 	pdc_reg_write(IRQ_ENABLE_BANK, index, enable);  in pdc_enable_intr()
92 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_disable()
101 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_enable()
110 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_mask()
118 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_unmask()
125  * GIC does not handle falling edge or active low. To allow falling edge and
126  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
127  * falling edge into a rising edge and active low into an active high.
130  * Level sensitive active low    LOW
134  * Level sensitive active High   HIGH
150  * @d: the interrupt data
160 	int pin_out = d->hwirq;  in qcom_pdc_gic_set_type()
189 		return -EINVAL;  in qcom_pdc_gic_set_type()
240 		if (pin >= region->pin_base &&  in get_parent_hwirq()
241 		    pin < region->pin_base + region->cnt)  in get_parent_hwirq()
242 			return (region->parent_base + pin - region->pin_base);  in get_parent_hwirq()
251 	if (is_of_node(fwspec->fwnode)) {  in qcom_pdc_translate()
252 		if (fwspec->param_count != 2)  in qcom_pdc_translate()
253 			return -EINVAL;  in qcom_pdc_translate()
255 		*hwirq = fwspec->param[0];  in qcom_pdc_translate()
256 		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;  in qcom_pdc_translate()
260 	return -EINVAL;  in qcom_pdc_translate()
264 			  unsigned int nr_irqs, void *data)  in qcom_pdc_alloc()  argument
266 	struct irq_fwspec *fwspec = data;  in qcom_pdc_alloc()
291 	parent_fwspec.fwnode      = domain->parent->fwnode;  in qcom_pdc_alloc()
308 			       unsigned int nr_irqs, void *data)  in qcom_pdc_gpio_alloc()  argument
310 	struct irq_fwspec *fwspec = data;  in qcom_pdc_gpio_alloc()
338 	parent_fwspec.fwnode      = domain->parent->fwnode;  in qcom_pdc_gpio_alloc()
366 	n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));  in pdc_setup_pin_mapping()
368 		return -EINVAL;  in pdc_setup_pin_mapping()
374 		return -ENOMEM;  in pdc_setup_pin_mapping()
378 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
383 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
388 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
414 		return -ENXIO;  in qcom_pdc_init()
420 		ret = -ENXIO;  in qcom_pdc_init()
426 		pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);  in qcom_pdc_init()
435 		ret = -ENOMEM;  in qcom_pdc_init()
446 		ret = -ENOMEM;  in qcom_pdc_init()