Lines Matching +full:8 +full:bit
19 /* 32MB = 8xFBPT_entry */
20 #define CIO2_MAX_LOPS 8
34 /* Register and bit field definitions */
50 #define CIO2_CSIRX_IF_CONFIG_FLAG_ERROR BIT(2)
58 (CIO2_REG_CSIRX_BASE + 0x2c + 8 * (lane))
60 (CIO2_REG_CSIRX_BASE + 0x30 + 8 * (lane))
67 #define CIO2_REG_MIPIBE_FORCE_RAW8_ENABLE BIT(0)
68 #define CIO2_REG_MIPIBE_FORCE_RAW8_USE_TYPEID BIT(1)
88 /* IRQ registers are 18-bit wide, see cio2_irq_error for bit definitions */
102 #define CIO2_CGC_CSI2_TGE BIT(0)
103 #define CIO2_CGC_PRIM_TGE BIT(1)
104 #define CIO2_CGC_SIDE_TGE BIT(2)
105 #define CIO2_CGC_XOSC_TGE BIT(3)
106 #define CIO2_CGC_MPLL_SHUTDOWN_EN BIT(4)
107 #define CIO2_CGC_D3I3_TGE BIT(5)
108 #define CIO2_CGC_CSI2_INTERFRAME_TGE BIT(6)
109 #define CIO2_CGC_CSI2_PORT_DCGE BIT(8)
110 #define CIO2_CGC_CSI2_DCGE BIT(9)
111 #define CIO2_CGC_SIDE_DCGE BIT(10)
112 #define CIO2_CGC_PRIM_DCGE BIT(11)
113 #define CIO2_CGC_ROSC_DCGE BIT(12)
114 #define CIO2_CGC_XOSC_DCGE BIT(13)
115 #define CIO2_CGC_FLIS_DCGE BIT(14)
119 #define CIO2_D0I3C_I3 BIT(2) /* Set D0I3 */
120 #define CIO2_D0I3C_RR BIT(3) /* Restore? */
134 * Interrupt on completion bit, Eg. DMA 0-3 maps to bit 0-3,
135 * DMA4 & DMA5 map to bit 4 ... DMA18 & DMA19 map to bit 11 Et cetera
143 #define CIO2_INT_IOIE BIT(22)
144 #define CIO2_INT_IOOE BIT(23)
145 #define CIO2_INT_IOIRQ BIT(24)
152 #define CIO2_PBM_ARB_CTRL_LE_EN BIT(7)
154 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN_SHIFT 8
159 #define CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT 8
161 #define CIO2_PBM_WMCTRL1_TS_COUNT_DISABLE BIT(31)
169 #define CIO2_PBM_WMCTRL2_LWM_2CK_SHIFT 8
174 #define CIO2_PBM_WMCTRL2_DYNWMEN BIT(28)
175 #define CIO2_PBM_WMCTRL2_OBFF_MEM_EN BIT(29)
176 #define CIO2_PBM_WMCTRL2_OBFF_CPU_EN BIT(30)
177 #define CIO2_PBM_WMCTRL2_DRAINNOW BIT(31)
181 #define CIO2_PBM_FOPN_ABORT(n) (0x1 << 8 * (n))
182 #define CIO2_PBM_FOPN_FORCE_ABORT(n) (0x2 << 8 * (n))
183 #define CIO2_PBM_FOPN_FRAMEOPEN(n) (0x8 << 8 * (n))
185 #define CIO2_LTRCTRL_LTRDYNEN BIT(16)
186 #define CIO2_LTRCTRL_LTRSTABLETIME_SHIFT 8
188 #define CIO2_LTRCTRL_LTRSEL1S3 BIT(7)
189 #define CIO2_LTRCTRL_LTRSEL1S2 BIT(6)
190 #define CIO2_LTRCTRL_LTRSEL1S1 BIT(5)
191 #define CIO2_LTRCTRL_LTRSEL1S0 BIT(4)
192 #define CIO2_LTRCTRL_LTRSEL2S3 BIT(3)
193 #define CIO2_LTRCTRL_LTRSEL2S2 BIT(2)
194 #define CIO2_LTRCTRL_LTRSEL2S1 BIT(1)
195 #define CIO2_LTRCTRL_LTRSEL2S0 BIT(0)
219 #define CIO2_CDMAC0_FBPT_WIDTH_SHIFT 8
220 #define CIO2_CDMAC0_FBPT_NS BIT(25)
221 #define CIO2_CDMAC0_DMA_INTR_ON_FS BIT(26)
222 #define CIO2_CDMAC0_DMA_INTR_ON_FE BIT(27)
223 #define CIO2_CDMAC0_FBPT_UPDATE_FIFO_FULL BIT(28)
224 #define CIO2_CDMAC0_FBPT_FIFO_FULL_FIX_DIS BIT(29)
225 #define CIO2_CDMAC0_DMA_EN BIT(30)
226 #define CIO2_CDMAC0_DMA_HALTED BIT(31)
247 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_CD (1 << 8)
252 #define CIO2_INT_EXT_IE_ECC_RE(n) (0x01 << (8 * (n)))
253 #define CIO2_INT_EXT_IE_DPHY_NR(n) (0x02 << (8 * (n)))
254 #define CIO2_INT_EXT_IE_ECC_NR(n) (0x04 << (8 * (n)))
255 #define CIO2_INT_EXT_IE_CRCERR(n) (0x08 << (8 * (n)))
256 #define CIO2_INT_EXT_IE_INTERFRAMEDATA(n) (0x10 << (8 * (n)))
257 #define CIO2_INT_EXT_IE_PKT2SHORT(n) (0x20 << (8 * (n)))
258 #define CIO2_INT_EXT_IE_PKT2LONG(n) (0x40 << (8 * (n)))
259 #define CIO2_INT_EXT_IE_IRQ(n) (0x80 << (8 * (n)))
261 #define CIO2_PXM_FRF_CFG_FNSEL BIT(0)
262 #define CIO2_PXM_FRF_CFG_FN_RST BIT(1)
263 #define CIO2_PXM_FRF_CFG_ABORT BIT(2)
265 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NR BIT(8)
266 #define CIO2_PXM_FRF_CFG_MSK_ECC_RE BIT(9)
267 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NE BIT(10)
269 #define CIO2_PXM_FRF_CFG_MASK_CRC_THRES BIT(13)
270 #define CIO2_PXM_FRF_CFG_MASK_CSI_ACCEPT BIT(14)
271 #define CIO2_PXM_FRF_CFG_CIOHC_FS_MODE BIT(15)
295 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_B -8
398 #define CIO2_FBPT_CTRL_VALID BIT(0)
399 #define CIO2_FBPT_CTRL_IOC BIT(1)
400 #define CIO2_FBPT_CTRL_IOS BIT(2)
401 #define CIO2_FBPT_CTRL_SUCCXFAIL BIT(3)