1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
41 /* Endpoint Bus and Device Number Register */
108 					(((aperture) - 2) << ((bar) * 8))
129 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
134 	(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
139 #define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \  argument
140 	(((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
142 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
166 #define  CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \  argument
167 	((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
169 /* Region r AXI Region Base Address Register 0 */
174 	(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
176 /* Region r AXI Region Base Address Register 1 */
180 /* Root Port BAR Inbound PCIe to AXI Address Translation Register */
185 	(((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
189 /* AXI link down register */
201 	RP_BAR_UNDEFINED = -1,
214 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
270  * struct cdns_pcie - private data for Cadence PCIe controller drivers
274  * @bus: In Root Complex mode, the bus number
290  * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
316  * struct cdns_pcie_epf - Structure to hold info about endpoint function
324  * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
328  * @ob_addr: base addresses in the AXI bus where the outbound regions start
329  * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
333  *		  IRQ) TLP through the PCIe bus.
365 	writel(value, pcie->reg_base + reg);  in cdns_pcie_writel()
370 	return readl(pcie->reg_base + reg);  in cdns_pcie_readl()
387 	return (val >> (8 * offset)) & ((1 << (size * 8)) - 1);  in cdns_pcie_read_sz()
407 	mask = ~(((1 << (size * 8)) - 1) << (offset * 8));  in cdns_pcie_write_sz()
417 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;  in cdns_pcie_rp_writeb()
425 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;  in cdns_pcie_rp_writew()
432 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;  in cdns_pcie_rp_readw()
441 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;  in cdns_pcie_ep_fn_writeb()
449 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;  in cdns_pcie_ep_fn_writew()
457 	writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);  in cdns_pcie_ep_fn_writel()
462 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;  in cdns_pcie_ep_fn_readw()
469 	return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);  in cdns_pcie_ep_fn_readl()
474 	if (pcie->ops->start_link)  in cdns_pcie_start_link()
475 		return pcie->ops->start_link(pcie);  in cdns_pcie_start_link()
482 	if (pcie->ops->stop_link)  in cdns_pcie_stop_link()
483 		pcie->ops->stop_link(pcie);  in cdns_pcie_stop_link()
488 	if (pcie->ops->link_up)  in cdns_pcie_link_up()
489 		return pcie->ops->link_up(pcie);  in cdns_pcie_link_up()
496 void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
504 static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,  in cdns_pci_map_bus()  argument